Help troubleshooting mic build

[ccaudle]

After the drain resistor, it reads 1.6V. And it reads 1.4v at the source resistor.

Is the power supply still at 29V? If the source and drain resistors are still as marked in the schematic, those voltages do not indicate the same current through the 39k and 6k8 resistors, but there is no where else for DC current to flow, it has to be the same in source and drain.

Im measuring 0 at the source and ~29V at the drain.

In that original condition it indicated no current flow, so both ends of the source resistor were at 0V, and both ends of the drain resistor were at 29V.

Once the JFET is biased on, current will flow through the drain resistor, into the drain, out the source, and through the source resistor. At that point the voltages across each resistor will be V=I*R, current multiplied by resistance. Since the current has to be the same through drain and source:
(29V-Vdrain)/29k = Vsource/6k754
The "6k754" is the 6k8 resistor in parallel with the 1M resistance of the pot.

So with 1.6V at the drain that would be (29-1.6)/29k = 0.9mA
With 1.4V at the source that would be 1.4/6.754k = 0.2mA

So either the measurements are not correct, the resistors are not the values you think, or 0.7mA of current is going somewhere other than through the JFET.

 

[jp8]

I've read the whole thread again and up to now, none of the information seems to make any sense, is contradictory, or is physically impossible. Before summarizing the things that confused me (and others), some questions about the circuit and how you built it:

• Nodes g1...g5 represent ground. I assume you tied them all together, but if you follow this schematic exactly to design a PCB layout in, e.g., Kicad or Altium or any other ECAD package for that matter, all these nodes would not connect to each other. Anyway, I find this a very weird way of drawing a schematic and confusing, at the very least.
• T5 connects to the capsule, but if I were to take the diagram very literally and follow it blindfolded to build, the ground terminal of the capsule would be floating in mid-air as there is no such connection explicitly drawn. Did you connect the capsule ground to either the ground net on the PCBA or to the chassis? And if it is connected to the chassis, is there a connection between XLR pin 1 and the mic chassis, as depicted to the left of nodes T1/g4? Without this capsule ground connection, it would explain why there is no sound from it (assuming the circuit is properly built and biased, etc.).

OK, so let's assume for now the ground connections are all as they should be. And let's assume you built the circuit exactly as depicted in the schematic, then let me summarize what I see as confusing or contradictory:

• If the Source voltage is at 0V, it would mean there is no bias current running. You said audio is coming through, assumingly applied to node T5 (Gate), and assumingly through a 30-100pF cap to simulate a capsule and to avoid the generator output from disrupting the JFET bias. But without drain-source current flowing, there should be no signal at the output, or it should be heavily distorted. Did you just listen to the output signal or watch it on a 'scope to see if there is any distortion?
• In your first post, you said there's 28V on the Drain, and 29V on the R1-C3-R7 net. That would indicate there is a current flowing through the JFET, but it's just way too low. In post #24, you write there's ~29V at the Drain. This is contradicting information. But still, with 29V on the Drain, there should be current running through R7 (and hence, through R1, Q1, R2), because assumingly there is 30V on the Zener Z1. Orrrrr, this assumption is just plain wrong and the current through Z1 is too low to establish the nominal 30V. Or the zener has a negative tolerance and is on 29V. To find out if there's really a bias current flowing or not, I would suggest you measure the zener voltage and all voltages across R7, R1, drain-to-source of Q1 and across R2. The sum of these voltages should equal the zener voltage. Or maybe just note down the voltages on all of the circuit nodes and write them on the schematic. Then post this schematic. And write down all the voltages exactly as displayed on the DVM, without rounding them off.
• As already pointed out before, the voltages you measured on the Gate do not make sense. You said you measured 2.4V on the Gate, but this cannot be measured with a normal DVM with e.g. 10M input impedance. But even if you would shunt the 1G resistor with a low resistance just for the voltage measurement on the Gate, it is physically impossible to measure 2.4V on the Gate if the Source is at 0V. Or C4 must be leaking (cracking?), but then the Drain voltage would not be at 28-29V.

Next to writing down all the node voltages, could you also upload pictures of the top and bottom sides of your PCBA? If possible, revealing the direction of the diodes and elcaps, the color codes on the resistors etc. or any other detail that could help us diagnose the fault.

Finally, a last word on C1: depending on your transformer and personal preference, you may want to increase the value of C1 to a much larger value than 1uF as depicted in the schematic or the 470nF that you use. You can read more about this here: https://sound-au.com/articles/audio-xfmrs.htm. I recently built some KM84 variants and used Aliexpress ASTDS T8 7:1 transformers. I did some frequency response measurements with various coupling caps, of which you'll find the REW graphs attached in a zip file. You can see a resonant bump with smaller cap values and increasing distortion. But having said that, this could be something you'd actually want. For a "transparent" low THD mic however, you would want larger capacitor values. I understand this is probably not your first concern right now, but I just wanted to mention it.

Good luck, and I hope you'll get the issue fixed.

Jan

 

[skyy7]

I've read the whole thread again and up to now, none of the information seems to make any sense, is contradictory, or is physically impossible. Before summarizing the things that confused me (and others), some questions about the circuit and how you built it:

• Nodes g1...g5 represent ground. I assume you tied them all together, but if you follow this schematic exactly to design a PCB layout in, e.g., Kicad or Altium or any other ECAD package for that matter, all these nodes would not connect to each other. Anyway, I find this a very weird way of drawing a schematic and confusing, at the very least.
• T5 connects to the capsule, but if I were to take the diagram very literally and follow it blindfolded to build, the ground terminal of the capsule would be floating in mid-air as there is no such connection explicitly drawn. Did you connect the capsule ground to either the ground net on the PCBA or to the chassis? And if it is connected to the chassis, is there a connection between XLR pin 1 and the mic chassis, as depicted to the left of nodes T1/g4? Without this capsule ground connection, it would explain why there is no sound from it (assuming the circuit is properly built and biased, etc.).

OK, so let's assume for now the ground connections are all as they should be. And let's assume you built the circuit exactly as depicted in the schematic, then let me summarize what I see as confusing or contradictory:

• If the Source voltage is at 0V, it would mean there is no bias current running. You said audio is coming through, assumingly applied to node T5 (Gate), and assumingly through a 30-100pF cap to simulate a capsule and to avoid the generator output from disrupting the JFET bias. But without drain-source current flowing, there should be no signal at the output, or it should be heavily distorted. Did you just listen to the output signal or watch it on a 'scope to see if there is any distortion?
• In your first post, you said there's 28V on the Drain, and 29V on the R1-C3-R7 net. That would indicate there is a current flowing through the JFET, but it's just way too low. In post #24, you write there's ~29V at the Drain. This is contradicting information. But still, with 29V on the Drain, there should be current running through R7 (and hence, through R1, Q1, R2), because assumingly there is 30V on the Zener Z1. Orrrrr, this assumption is just plain wrong and the current through Z1 is too low to establish the nominal 30V. Or the zener has a negative tolerance and is on 29V. To find out if there's really a bias current flowing or not, I would suggest you measure the zener voltage and all voltages across R7, R1, drain-to-source of Q1 and across R2. The sum of these voltages should equal the zener voltage. Or maybe just note down the voltages on all of the circuit nodes and write them on the schematic. Then post this schematic. And write down all the voltages exactly as displayed on the DVM, without rounding them off.
• As already pointed out before, the voltages you measured on the Gate do not make sense. You said you measured 2.4V on the Gate, but this cannot be measured with a normal DVM with e.g. 10M input impedance. But even if you would shunt the 1G resistor with a low resistance just for the voltage measurement on the Gate, it is physically impossible to measure 2.4V on the Gate if the Source is at 0V. Or C4 must be leaking (cracking?), but then the Drain voltage would not be at 28-29V.

Next to writing down all the node voltages, could you also upload pictures of the top and bottom sides of your PCBA? If possible, revealing the direction of the diodes and elcaps, the color codes on the resistors etc. or any other detail that could help us diagnose the fault.

Finally, a last word on C1: depending on your transformer and personal preference, you may want to increase the value of C1 to a much larger value than 1uF as depicted in the schematic or the 470nF that you use. You can read more about this here: https://sound-au.com/articles/audio-xfmrs.htm. I recently built some KM84 variants and used Aliexpress ASTDS T8 7:1 transformers. I did some frequency response measurements with various coupling caps, of which you'll find the REW graphs attached in a zip file. You can see a resonant bump with smaller cap values and increasing distortion. But having said that, this could be something you'd actually want. For a "transparent" low THD mic however, you would want larger capacitor values. I understand this is probably not your first concern right now, but I just wanted to mention it.

Good luck, and I hope you'll get the issue fixed.

Jan

I genuinely apologize if I was confusing... I did not realize how precise I had to be, as rounding things caused confusion. I also believe I was being inconsistent in measuring all the points and will ensure that does not happen moving forward. Again, I apologize, and I am truly grateful for everyone's help.

I have built this on Perfboard, increasing the possibility of user error during the build.

All the grounds are tied together, and the capsule was also grounded via the ground connections on the PCB, which is directly connected to the ground pin on the XLR.

The test signal was injected to the gate with the capsule installed and also connected to the gate. The output of the mic was then recorded and the THD was analyzed in a DAW. The THD was fairly low and this was consistent with the sound of the recorded output having fairly minimal distortion.

As for the voltage readings... I am getting a zener voltage of exactly 29.00v. The zener diode being used is the TZX30A. Across R7 I am getting a voltage reading of 0V. Across R1, I am also getting 0.01V. Drain to source I am getting exactly 28.89V.

Regarding the gate voltage, I am getting 2.355V. I am not sure if this is correct. I am only putting the negative lead from the DMM at ground and the positive lead to the gate. From my understanding, this should not be possible as the impedance at the gate is too high. However, this is just something I observed. This is consistent with and without the existence of C4.

I am unable to take photos at the time. However, I have confirmed the diode is pointed the correct way, and the resistors are all the correct values aside from R2, which is currently a 2.2k resistor... This was done to try to get the JFET to bias. I seem to have made the stupid mistake of misplacing the original 6.8k resistor I had. To confirm, I had this same issue both when R2 was 2.2k and 6.8k.

The reading and analysis of the effect of the C1 capacitor on the THD in a transformer circuit was also very interesting and something I did not know. This microphone is not intended to be a transparent microphone and I was hoping to mess with the signal in the circuit just as a test/fun project. I will keep this in mind for future transformer builds.

Again, I would like to apologize genuinely. This community has really helped me a lot while going through my first mic builds and I do not want to do anything to disrespect or waste anyone's time.

 

[jp8]

This helps, thanks!

Maybe I cracked the nut... My best guess at the moment:

• The JFET gate is not connected to the capsule but connects to the 6k8 (or 2k2).
• Source or Drain connects to the capsule.
• Source or Drain connects to R1/C4/C1.

This reverse biases the Gate to Source/Drain canal silicon. Hence, no voltage on the 6k8 and no bias current, except a very, very low current through the 1G.

It also explains the practically undistorted output signal when feeding a signal to the Gate: it passes the Drain/Source canal resistance to the relatively high input impedance of the transformer. Disconnect the capsule and feed the signal through a 39...100pF capacitor and you're likely to hear/measure nothing.

And finally, it explains why you measure a voltage on the casule node. Could be any voltage, though. Depends on JFET channel resistance and DVM input impedance. If you have a second DVM at hand, you could try and measure simultaneously on the capsule node and on the C1/C4/R1 node. That voltage should drop somewhat upon connecting the other DVM to the capsule node.

And if you happen to have a component tester that automatically identifies the component and which test lead gies to which component terminal, you can figure out the real pinning of the JFET. Source and Drain can be swapped, by the way. These parts are symetrical.

Cheers, Jan

 

[Khron]

Source and Drain can be swapped, by the way. These parts are symetrical.

I've read that in many places, but that still means that the gate-to-source voltage affects the bias (despite the bidirectional nature of the conduction channel), right?

 

[gyraf]

Yes, but you decide which one gets to be the source, by where you connect it in the circuit

 

[Drosselmeier]

Source and Drain can be swapped, by the way.

I tried to do this in the 87Ai circuit, I just got it wrong. Did not work )) J117 FET. 2SK117 FET.

 

[Voyager10]

Can we start from basics, by testing the FETs out of circuit?

Here's a setup for testing the Idss of a J305 FET:



It's very simple:
* Source and gate (in rows 26 and 24, respectively) are shorted together, and connected to power supply ground.
* The drain (row 25, middle leg of the JFET) is connected via a 1K resistor to power supply positive.

I'm then applying 12V power to the circuit (although a 9V battery would do), and measuring the voltage across the 1K resistor (rows 20 and 25) with a DMM. I'm getting about 5.2V, corresponding to an Idss of 5.2mA.

The InterFET J305 datasheet gives Idss as 1-8mA, so any reading in the 1 to 8V range indicates a basically-working FET.

 

[jp8]

I tried to do this in the 87Ai circuit, I just got it wrong. Did not work )) J117 FET.

The J117 (or 2SJ117?) is a P-MOSFET, which has a body diode. Hence, Drain and Source cannot be swapped. I do not know the J117 as a JFET. Do you have a datasheet?

Jan

 

[Drosselmeier]

I'm sorry, I corrected it

 

[jp8]

I'm sorry, I corrected it

No worries...

I did not find a clue in de 2SK117 datasheet from which I could conclude the device is symmetrical or not. But if you tried and it doesn't work, it must be an asymmetrical JFET. If I'm not mistaken, the through-hole version of the MXL770 has the D and S of the 2SK170 swapped. So it could work, but apparently not for any JFET.

Anyway, your remark made me curious and I tested 5 different SMT JFETs that I typically use in my circuits (2SK208, 2SK209, IF4500, IF170 and 2SK2394). I used Voyager10's setup. Swapping D and S yielded the same Idss on all 5 parts. So at least these seem to be symmetrical.

Jan

 

[skyy7]

Can we start from basics, by testing the FETs out of circuit?

Here's a setup for testing the Idss of a J305 FET:

View attachment 128018

It's very simple:
* Source and gate (in rows 26 and 24, respectively) are shorted together, and connected to power supply ground.
* The drain (row 25, middle leg of the JFET) is connected via a 1K resistor to power supply positive.

I'm then applying 12V power to the circuit (although a 9V battery would do), and measuring the voltage across the 1K resistor (rows 20 and 25) with a DMM. I'm getting about 5.2V, corresponding to an Idss of 5.2mA.

The InterFET J305 datasheet gives Idss as 1-8mA, so any reading in the 1 to 8V range indicates a basically-working FET.

I just tested the JFETs I was using, and I am getting 6.19V and 3.82V for the 2 JFETs I was testing.

Can I assume those readings show a working JFET and the pin out I have been using is also correct?

 

[skyy7]

This helps, thanks!

Maybe I cracked the nut... My best guess at the moment:

• The JFET gate is not connected to the capsule but connects to the 6k8 (or 2k2).
• Source or Drain connects to the capsule.
• Source or Drain connects to R1/C4/C1.

This reverse biases the Gate to Source/Drain canal silicon. Hence, no voltage on the 6k8 and no bias current, except a very, very low current through the 1G.

It also explains the practically undistorted output signal when feeding a signal to the Gate: it passes the Drain/Source canal resistance to the relatively high input impedance of the transformer. Disconnect the capsule and feed the signal through a 39...100pF capacitor and you're likely to hear/measure nothing.

And finally, it explains why you measure a voltage on the casule node. Could be any voltage, though. Depends on JFET channel resistance and DVM input impedance. If you have a second DVM at hand, you could try and measure simultaneously on the capsule node and on the C1/C4/R1 node. That voltage should drop somewhat upon connecting the other DVM to the capsule node.

And if you happen to have a component tester that automatically identifies the component and which test lead gies to which component terminal, you can figure out the real pinning of the JFET. Source and Drain can be swapped, by the way. These parts are symetrical.

Cheers, Jan

Yeah... I get nothing when I remove the capsule from the circuit and try to feed the signal through a 30pf capacitor...

I do believe you're correct. However, I can't find a short between these points using a continuity tester... Is there any better way to test it?

Also, could the problem be that I am using an unpolarized capacitor for C1? I don't see how it could be an issue yet I'm really unsure at this point.

 

[jp8]

I just tested the JFETs I was using, and I am getting 6.19V and 3.82V for the 2 JFETs I was testing.

Can I assume those readings show a working JFET and the pin out I have been using is also correct?

I think so, yes.

 

[jp8]

Yeah... I get nothing when I remove the capsule from the circuit and try to feed the signal through a 30pf capacitor...

I do believe you're correct. However, I can't find a short between these points using a continuity tester... Is there any better way to test it?

Also, could the problem be that I am using an unpolarized capacitor for C1? I don't see how it could be an issue yet I'm really unsure at this point.

I didn't immediately think of a short circuit, but rather a wrongly connected JFET. Capacitor type is not the issue: it has practically infinite resistance and will not affect DC bias of the circuit.

Another way to check if the JFET is properly connected in the circuit is as follows:

• Put your DMM in the diode/continuity checking mode.
• Leave the circuit unpowered.
• Connect the + lead of the DMM to the capsule node.
• Connect the - lead to the 6k8 node. The DMM should read between 600 and 750mV or so (a diode forward voltage).
• Do the same with the Drain node on the 39k resistor. The DMM should read a similar voltage.

If this is not the case, the JFET was not properly connected.

Jan

 

[Voyager10]

Those results are consistent with a working FET, although it doesn't conclusively prove which is gate and source, because they were connected together during the test.

Here's another test:



So:

• Power supply +ve (I used 12V again) goes directly to the middle pin ("drain", we hope)
• Power supply -ve goes to the "gate" pin, row 24
• The "source" pin (row 26) goes via a 1K resistor to power supply -ve and the "gate".

Once again, you can measure the voltage across the 1K resistor with a DMM. If you get some voltage (maybe 1-2V, I got 1.3V), all is well. Row 26 is the source and row 24 is the gate.

If you get 0V across the resistor, it's not working properly. It's possible row 26 is the gate and row 24 is the source.

 

[Voyager10]

If that goes OK, you can maybe try the following, on a breadboard or point-to-point wired:



Connect the source via a 6k8 resistor to ground, and the drain via a 39K to +30V, as in the original schematic.

Following the left-hand diagram, wire the gate to ground and measure all the voltages. You won't get exactly the same, but there should be a low voltage across the 6k8, just under 6x that voltage on the 39K, and a biggish voltage between drain and source.

Then wire the gate to the source and re-measure. You should get close to 0V between drain and source, and close to the voltages shown on the 6.8K and 39K resistors.

If that goes OK, you can transfer the FET to the real circuit and try to duplicate the measurements (to start with, hard-wire the gate to each end of the 6k8 resistor in turn). If it doesn't work, disconnect all the other components, check the stripboard for shorts, etc., until you've reduced it back to the circuit above.

 

[skyy7]

I didn't immediately think of a short circuit, but rather a wrongly connected JFET. Capacitor type is not the issue: it has practically infinite resistance and will not affect DC bias of the circuit.

Another way to check if the JFET is properly connected in the circuit is as follows:

• Put your DMM in the diode/continuity checking mode.
• Leave the circuit unpowered.
• Connect the + lead of the DMM to the capsule node.
• Connect the - lead to the 6k8 node. The DMM should read between 600 and 750mV or so (a diode forward voltage).
• Do the same with the Drain node on the 39k resistor. The DMM should read a similar voltage.

If this is not the case, the JFET was not properly connected.

Jan

Sorry about the late reply.

Using this, I found that the gate was actually on the rightmost pin of the JFET. My bad, @Khron. I think it was the one orientation I didn't check while flipping the FET... Anyway, using this, I get current across the JFET, and I am able to bias it, and everything works great. Thank you everyone for your patience and help!

 

[jp8]

No worries, skyy77. Great to hear that the problem has now been resolved. Enjoy using your microphone!

Jan

 

[Khron]

I think it was the one orientation I didn't check while flipping the FET.

Well how *DID* you "flip the FET" then?