Need help with a TLM 102 sized PCB for DIY LDC mic

[JohnRoberts]

The suggestion to put as much gain in the first stage as possible to improve S/N is not without compromise. Too much front end gain can cause headroom issues.
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I deleted a few posts that were stirring the pot... please play nice, and be kind.

JR

PS: I locked the thread because I just didn't feel like reading it last night. I read it today.. you're welcome.

 

[ccaudle]

Too much front end gain can cause headroom issues.

Both voltage, and potentially current available from the phantom power. 6dB voltage gain means twice the current delivered to the input impedance of the mic amp.

following low noise gain stages, rather than trying to do it in the mic

If you can get the electronics quiet enough that the capsule noise dominates, then it won't matter, if you add gain in the mic or in the pre-amp the noise floor will be dominated by the capsule noise, so then it makes sense to have the mic buffer as unity gain for simplicity and sake of headroom.
There may be a conversation which can be had about noise spectrum and audibility and the difference between the spectrum of the electronic noise vs. capsule noise, looking at the noise on a frequency range basis rather than a single number of integrated noise level, but in any normal acoustic environment you are getting pretty deep into the area of questionable relevance at that point.

 

[edenooo]

The suggestion to put as much gain in the first stage as possible to improve S/N is not without compromise. Too much front end gain can cause headroom issues.
====
I deleted a few posts that were stirring the pot... please play nice, and be kind.

JR

PS: I locked the thread because I just didn't feel like reading it last night. I read it today.. you're welcome.

I was worried why it was locked!! I had one last question I'll post later and was worried I'd have to make a whole new post to ask it lol

 

[Itsme]

The suggestion to put as much gain in the first stage as possible to improve S/N is not without compromise. Too much front end gain can cause headroom issues.

Apologies if my comments were misleading. My suggestion is to put as much as possible of the total desired gain into the first stage as this would reduce the added noise of the following instances significantly. This is in particular valid if an active inverter stage is implemented.

 

[pmfalcman]

Yes I'm aware! I'm have space to add those, I just didnt want to have to work around them while routing

Do not put it out for too long. It'll bite you in the as..tounding place.
Best practice is: mounting points first. You cannot move them, you have to have mounting holes/points in given places.
THEN route around whatever you're connecting. No matter whether traces, wires, pipes or other.
Drilling through an IC is doable but causes noise issues or adversely influences FR.
But then again - I'm not familiar with this body, mounting might be simple and straightforward.

 

[edenooo]

Ok so- looks like the "OPA1642AIDR" (Pictured on the right) I used in my schematic is out of stock on JLCPCB and their suppliers, but they have a ton of the "OPA1642AIDGKR" available, this version uses a VSSOP-8 footprint instead of an SOIC-8 footprint, my question is- the numbers used are simply in reference to the pin being used for the same function, correct..? Meaning the 8 on the "AIDKGR" variant is the same 'function' as pin 7 on the "AIDR" version..? I see the version on the OPIC42 project seems to have the same 'pinout' as the "OPA1642AIDR" on the right.

Is this correct..? Or is there any some reason that I'm not able to use the "OPA1642AIDGKR" variant? They seem to be totally identical based on what I can read from the datasheets, but I'm rather inexperienced.

 

[edenooo]

Do not put it out for too long. It'll bite you in the as..tounding place.
Best practice is: mounting points first. You cannot move them, you have to have mounting holes/points in given places.
THEN route around whatever you're connecting. No matter whether traces, wires, pipes or other.
Drilling through an IC is doable but causes noise issues or adversely influences FR.
But then again - I'm not familiar with this body, mounting might be simple and straightforward.

I had originally routed with them in mind luckily, I had kept them at certain points and had just removed them temporarily so they weren't in the way while I was working, but I absolutely agree.

And mountng should be fairly simple, I'm very component at 3D printing and have the necessary tolerances for the circuit inside the body, despite how utterly tiny the body is.

 

[Khron]

my question is- the numbers used are simply in reference to the pin being used for the same function, correct..? Meaning the 8 on the "AIDKGR" variant is the same 'function' as pin 7 on the "AIDR" version..?

Google - "opa1642" - datasheet (should be among the first couple of results) - pinout should be within the first few pages.

 

[Itsme]

Ok so- looks like the "OPA1642AIDR" (Pictured on the right) I used in my schematic is out of stock

It looks like you are mixing it up. The 1642 is a dual, the 1641 is the single. The pin numbering across the package options of the 1641 is the same fortunately .

 

[edenooo]

It looks like you are mixing it up. The 1642 is a dual, the 1641 is the single. The pin numbering across the package options of the 1641 is the same fortunately .

HOW DOES THIS KIND OF THING KEEP HAPPENING

I must be actually going insane, thank you lol

 

[Itsme]

It's getting less with experience, but never goes completely away...ask me how I know .

 

[JohnRoberts]

Apologies if my comments were misleading. My suggestion is to put as much as possible of the total desired gain into the first stage as this would reduce the added noise of the following instances significantly. This is in particular valid if an active inverter stage is implemented.

It is a useful rule of thumb but as with most engineering decisions there can be competing interests.

JR

 

[Itsme]

It is a useful rule of thumb but as with most engineering decisions there can be competing interests.

Almost always...

 

[rogs]

As @Itsme has mentioned, you are confusing the OPA1641 and OPA1642 devices.

Couple of points....
The pin outs for the OPA1641:
• inverting input - pin 2
• non-inverting input - pin 3
• - ve supply (gnd) - pin 4
• output - pin 6
• +ve supply - pin 7
The other pins are not connected.

OPA1642: all 8 pins are used, but only pins 2, 3 and 4 perform the same function as the OPA1641.
OPA1641 and OPA 1642 are not interchangeable.

• The SOIC and VSSOP footprints have different pin spacing, and are also not interchangeable.

 

[edenooo]

As @Itsme has mentioned, you are confusing the OPA1641 and OPA1642 devices.

Couple of points....
The pin outs for the OPA1641:
• inverting input - pin 2
• non-inverting input - pin 3
• - ve supply (gnd) - pin 4
• output - pin 6
• +ve supply - pin 7
The other pins are not connected.

OPA1642: all 8 pins are used, but only pins 2, 3 and 4 perform the same function as the OPA1641.
OPA1641 and OPA 1642 are not interchangeable.

• The SOIC and VSSOP footprints have different pin spacing, and are also not interchangeable.

Yeah, can't believe I somehow completely overlooked that despite how much I've looked at these schematics.

 

[Khron]

Yeah, can't believe I somehow completely overlooked that despite how much I've looked at these schematics.

Google - "opa1642" - datasheet (should be among the first couple of results) - pinout should be within the first few pages.

Straight from the horse's mouth But I guess that would've made too much sense(?)...