12AT7 Phase splitter

[Mikaeel]

Hello!
I understand tubes/valves are not ideal. But, my experience is beyond this problem.
The following splitter I calculated has near unity gain amplification ratio.



The only problem is that the amplitudes of the signals do not match:


Lower half:



I know it's a noob question, but is there any way to minimise these differences?

 

[ruffrecords]

This is because the two output impedances are different and the loads are too heavy. Change both loads (R8 and R5) from 10K to 100K and see what happens.

Cheers

Ian

 

[Matador]

https://valvewizard.co.uk/cathodyne.pdf

I think the bottom phase will always be ~5% less due to the extra 400 ohms, yes?

Notice in Merlin's explanation, the gain equation assumes that the load impedance is >> the product of uZ (mu times the anode/cathode impedances), however you have a 10k load which means the gain will be impacted.

 

[Mikaeel]

Change both loads (R8 and R5) from 10K to 100K and see what happens.

Unfortunately not helps:



Only the DC component on outputs raises:

Notice in Merlin's explanation, the gain equation assumes that the load impedance is >> the product of uZ (mu times the anode/cathode impedances), however you have a 10k load which means the gain will be impacted.

I'f understand it right, I'll be unable to have 10k output impedance...
If my calculations are correct, with Ra and Rk = 50k , Zout-anode=8.33kΩ and Zout-cathode= 819.6 ohm....
I ommited the additional 400 ohms but the difference raises too:

 

[ruffrecords]

Some of this may be simulation artefacts. I notice the waveforms are not symmetric which they should be if capacitor coupled. Can you post the .asc file

Cheers

Ian

 

[Mikaeel]

Thanks for the help Ian,

Please see attached zip archive.

 

[ruffrecords]

OK, I realise now that your plate and cathode resistors of 50K and your load resistors are 10K. This is the sorce of the problem and increasing the loads to 50K will not help much. But increasing them to 470K does pretty much fix the problem.

I also changed your trans sim to 50mS duration and 1uS step size as this give a much more readable display. I attach the modified .asc file (with a .txt extension). If you run the trans sim and plot V(out+) + V(out-) you get a plot of the difference between the two waveforms. I get about 80uV which seems close enough to me.

Cheers

ian

 

[Mikaeel]

Thanks Ian!

This is the sorce of the problem and increasing the loads to 50K will not help much. But increasing them to 470K does pretty much fix the problem.

Only what I noticed, if we increase duration to 200ms, the difference keeps raising again to 6mv.

On my first screenshot I used additional 400 ohm resistor, to match the level of the signal that comes from cathode. It gives the same difference of 6mv, but I'm afraid such load may make tube get too hot, and will such a stage be safe to use. Could you pllease check attached file below:

 

[merlin]

Your imbalance has nothing to do with the loading. The balance of the inverter is *perfect* as long as the loads are identical; Ohm's law guarantees it. The apparent imbalance is not an imbalance at all (your green and blue traces are identical in AC terms), it is a DC offset caused by the coupling caps charging from time zero. If you run the simulation long enough, you will see balance settles at perfection.

https://valvewizard.co.uk/cathodyne.pdf

 

[Mikaeel]

Thanks Merlin!

I thought so too! It should be identical, but this DC component (offset) does not disappear here. This is what makes me curious. I run the simulation for more than 6 seconds and it still keeps this 6mv od difference. I don't have years of experience in electronics design, but something is strange in this simulation with LTSpice, maybe the tube model is wrong (but I doubt it). Overall, what do you think about such a splitting stage as it is (to load 10k), I'm trying to evaluate if it will be possible to omit the output transformer. Does this stage not affect the operation of the triode, from a tube design perspective? Could this offset be caused by some kind of DC leakage? I understand that perfection doesn't exist, but for my understanding 6millivolts is somehow an unwanted difference for a balanced output.

 

[merlin]

A tiny residual difference in the visual height of the peaks will be due to even harmonic distortion, not imbalance -the wave is stretched on one side and squashed on the other.

What do you think about such a splitting stage as it is (to load 10k), I'm trying to evaluate if it will be possible to omit the output transformer

Do you mean this is for a line output? This would not be suitable as a line driver since the anode output will pick up way more ambient hum than the cathode output, so you'll lose all your CMRR at the far end of the cable. If you wanted to use this circuit you would need to buffer the two outputs.

 

[Mikaeel]

A 6mV difference in the visual height of the peak might simply be distortion -the wave is stretched on one side and squashed on the other.

This is what I really missed! Interesting how LTSpice calculates this. Here's the FFT analysis below:




Apart from harmonic distortion, the noise floor is quite low. So if this affects the disballance between outputs, my understanding is that it should be the same with solid state (op amp based) splitters.

Do you mean this is for a line output? This would not be suitable as a line driver since the anode output will pick up way more ambient hum than the cathode output, so you'll loose all your CMRR at the far end of the cable.

Yes I understand how it may sound. But I want to give a try, to experiment with shields, clean power sources, additional cancelling cirquits, etc...

 

[merlin]

Apart from harmonic distortion, the noise floor is quite low. So if this affects the disballance between outputs, my understanding is that it should be the same with solid state (op amp based) splitters.

The visual height of the peaks will always be different when you balance a signal that is asymmetrical around the horizontal axis, so yeah SS splitters will do the same. Here is an example for a totally distortionless circuit balancing a signal that is not visually symmetrical. This is not a defect, its how balanced signals are supposed to look; there is equal area underneath each half-cycle.

 

[Mikaeel]

Thank you Merlin. Could you please tell me if this is due to phase differences? What causes this imbalance? Or perhaps you can tell me in what range this asymmetry is acceptable? As I am passing an ideal sine wave through the splitter, it should cross at zero, which I am not currently seeing on the LTSpice graph. While your example is ideal


edit: Please ignore regarding crossing on zero. everything is ok!

 

[Cqwet Dbdfte]

At best a phase splitter will be "near perfect" and the harmonic descending sequence will be altered in the output transformer where the even order (nice) harmonics will be lost.
The more gain in the tube the better the performance. Try a high transconductance pentode like E180F.
What tubes are you driving with this splitter?
Also consider using a constant current source for a triode to get better linearity and closer to the rail voltage.
Grid loading of power tubes may call for a buffer/follower if driven into a positive region.

 

[Mikaeel]

the harmonic descending sequence will be altered in the output transformer where the even order (nice) harmonics will be lost.

The purpose of this experiment is to see how well the output resistors can be driven without a transformer, and how good the performance is with proper shielding.

The more gain in the tube the better the performance. Try a high transconductance pentode like E180F.
What tubes are you driving with this splitter?

I want to try 12AT7 (ECC82) tubes, too expensive nowadays, and I have 40-50 of them. What I see, if stage has more gain, the more noise and distortion it adds. For this reason I chose a gain factor close to 1. At least the simulation shows a very low noise floor (except THD).

Also consider using a constant current source for a triode to get better linearity and closer to the rail voltage.

I am probably going to say something very strange, but anyway, I want to experiment with a high frequency switching power supply and filter out all the noise it has above the human hearing range.
This circuit is a primitive DI box with no gain selector. It should accept huge input voltages without clipping, as modern pickups produce very hot signals.