HellfireStudios
Well-known member
Cgaines said:
Wire up the front diaphragm to FC Cap and the backplate to FC Body. Leave the other pads (RC) empty.
-James-
Neumann Vintage U87 Clone : Build Thread.
- Thread starter poctop
- Start date
Help Support GroupDIY Audio Forum:
Wire up the front diaphragm to FC Cap and the backplate to FC Body. Leave the other pads (RC) empty.
-James-
Hey thanks for the help HellfireStudios and Poctop! I took on this project as a learning experience and I believe I succeeded. This forum is a great tool for people who actually know what they are doing, to help out people who don't. I still have only grazed the surface but I'm sure this site will help me dig deeper. I would like to understand a little more why Dave can use this capsule in his 87 mic and have polar selections. Does his circuit have jumpers somewhere, that the other diaphragm is attached to, that allows the pattern selection? And this circuit doesn't?
HellfireStudios
Well-known member
The U-87 used a derivative of the K67 capsule that was used in the U-67. The only real difference is the backplates are electrically isolated from each other by a plastic spacer. The vintage U-87 circuit requires this isolated backplate design for polar pattern selection. Dave Thomas is probably not sticking as closely to the original U-87 circuit as this project does. Most other U-87 style mics use the K67 style capsule.
Cgaines
Hellfire is correct the 67 and 87 are very close in terms of construction and hole pattern. For some reason on the 87 type Neumann decided to isolate them, so if you take your dmm to check continuity you wont see a connection from one backplate to the other. this is done with a plastic spacer and some very odd screws. The screws that hold the backplates together are sheilded so when they pass through the plate it doesnt touch the brass. I actually am building both 67 and 87 style capsules. If you want I could turn your 67 to an 87 pretty quickly. Send me a pm if your interested.
Eric
Hellfire is correct the 67 and 87 are very close in terms of construction and hole pattern. For some reason on the 87 type Neumann decided to isolate them, so if you take your dmm to check continuity you wont see a connection from one backplate to the other. this is done with a plastic spacer and some very odd screws. The screws that hold the backplates together are sheilded so when they pass through the plate it doesnt touch the brass. I actually am building both 67 and 87 style capsules. If you want I could turn your 67 to an 87 pretty quickly. Send me a pm if your interested.
Eric
![Electronics Soldering Iron Kit, [Upgraded] Soldering Iron 110V 90W LCD Digital Portable Soldering Kit 180-480℃(356-896℉), Welding Tool with ON/OFF Switch, Auto-sleep, Thermostatic Design](https://m.media-amazon.com/images/I/41gRDnlyfJS._SL500_.jpg)
HellfireStudios
Well-known member
Tskguy, the AK-67 capsule is 35mm in diameter unlike the Peluso's, etc. that are 34mm. Are your plastic spacers the right size to modify Cgaines' capsule? I would hate to see all that shipping/labor paid for, with nothing in return.
-James-
-James-
HellfireStudios
Well-known member
I'm glad to hear it. I hope it works out. On another note, could you do reskins of chinese capsules that have been damaged, or is the inconsistency of chinese stuff a deterrent? Thanks.
I got back in town last night and rewired my capsule and it worked! Sounds very cool and dark. Darker than anything I have. I am having some low level hum that's bothering me. Its only when I have to really crank the amp. Any Ideas? It looks as though the boards are grounded to the body well. The mounting screws are snug and making contact. I tried adding a wire from the "gndlink" to the screw but that didn't help either. Now I'm out of ideas...
I just finally built up one of my 2 mics. I used vintage capsule and transformer. I did a small vocal test comparing it to a 414 EB and a Sony c 38. Both mics that are very nice. I have to say the 87 sounds wonderful. I can't wait to give it some use and see how I like it in day to day work.
Thanks Dan and everyone else who has been so helpful in making this happen.
Thanks Dan and everyone else who has been so helpful in making this happen.
- Joined
- Jul 15, 2009
- Messages
- 2,306
Cgaines said:
"Swapped out the 220pf (C6) for a Wima 100pf," quote from GeekMacdaddy this is likely reduce negative feedback and undarken a bit if you would like to try ,
the Value of C6 is based on the original K87 sound. As for the hum check your ground scheme and mic shielding and bottom base nut to be tight
Cheers,
Dany,
Matador
Well-known member
Ok here are some more notes about this circuit that I've formulated over the last few days. The equations that govern JFET behavior (and this circuit as an extension), are non-linear and difficult to summarize succinctly. However there are a few broad generalizations that can be made.
First off, we can reason a bit about operating points based on the original Neumann design. First off, it stands to reason that the target was that the drain voltage would sit at roughly half the supply voltage (in this case, this is the voltage coming out of R14, and shown to be 21V). If this is true, then half of this is 10.5V. With a 47K drain resistor, this gives a quiescent bias current of 223uA. I'm guessing Neumann selected 225uA which is really close.
With the drain bias and drain resistor selected, we need to figure out the idling point next. I'll spare the detailed math, but you essentially look at the VGS / IDS transfer curve, and find a point roughly around the point that intersects 225uA. I've found for the nominal 2N3819, this voltage is roughly -3.4V (but given JFET parameter swing, can be anyplace from -0.2V up to damn near -7V!). If you measure the IDSS and IDS points you can calculate VP, then use the equations I provided earlier to find the VGS that intersects with the 225uA point with a spreadsheet.
So if the nominal 2N3819 has a VGS at -3.4V at a quiescent current of 225uA, then the source resistor needs to be 15.2K. This will place the source voltage at 3.4V. With a 47K drain resistor, the drain will idle at 10.5V given these nominal JFET conditions, which I have confirmed with a SPICE simulation.
Herein lies the first problem with this circuit: in order to be in the saturation region, the VDS voltage must be held above VP, otherwise the JFET is operating in it's ohmic (or triode) region. In this region, the drain->source current starts to depend on VDS (and not just on VGS). As the VDS falls, the transistor impedance rises, which can be thought of as a "softening" of the pulling ability of the JFET down towards it's source terminal (it essentially becomes a VCR, or "voltage controlled resistor").
In any case, we must maintain VDS at greater than VP (which in this case is 4V for the nominal 2N3819). Now while the trouble is on the downward slope for output (meaning on the upward slope on the input, given this is an inverting stage), due to the action of gm against RD, the drain voltage will fall "faster" than the source voltage. If this difference falls below VP, the waveform will start suffering a lot of THD.
You can see this for the nominal U87 circuit with a nominal JFET in the SPICE plot below:
which is a plot of VDS with an input signal of 1kHz, 200mV peak to peak. You can see that as the output signal falls below the 4V threshold, the signal flattens out.
This means that the VP level greatly reduces the amount of gain we can realize while still maintaining low distortion. Although the gain calculates at roughly 35, we can really only make use of the first 88mV of input signal before the stage begins to run out of signal swing headroom.
There are two ways this can be mitigated: the first is to run higher quiescent current. This has the effect of reducing the VGS bias, which means that the source resistor can be smaller. With less VGS bias, we can swing more signal. This has the secondary effect of reducing gain however, but we do get more input headroom.
The other way is to jack up the VDD voltage from 21V. For example, if we raise this up to 30V, and idle at 15V, then we can raise up the drain resistor to 67K and have a few more volts of headroom before we start to run into trouble. We have to be careful however, as if we exceed the maximum drain to gate voltage (25V for the 2N3819) we get into more trouble. 30V is about as high as one can go.
Here is the same plot with 30V VDD, 15V idle:
Looks much cleaner, gain is slightly higher as well (50 versus 35, with a larger input swing too). Output impedance is higher however, which means we have to think about dampening into the output transformer too!
The fundamental problem here is that with a nominal JFET, we are operating too far away from IDSS. With IDSS also comes lower VP, which means less headroom.
Here is the same idea with a minimal JFET (2mA IDSS, VP of -0.22V). Gain is up another full order of magnitude (around 100), and we have tons more output swing to use up because VGS is so low (about -0.15V). Gain is up because we are so much closer to IDSS in the quiescent state. The simulation shows that 30mV at the input swings nearly 7V at the output.
However input headroom is tiny: roughly 50mV will take the output to the rail. This may be ok if you are only room miking at a distance, but this would distort heavily on loud sources I am guessing.
What I'll do next is post a chart of IDSS and VP, and what the gain and headroom look like. That way, you can hand select a JFET to go with whatever operation you like. I'll also post the source resistor values so that those without a scope can get very close to the ideal value.
First off, we can reason a bit about operating points based on the original Neumann design. First off, it stands to reason that the target was that the drain voltage would sit at roughly half the supply voltage (in this case, this is the voltage coming out of R14, and shown to be 21V). If this is true, then half of this is 10.5V. With a 47K drain resistor, this gives a quiescent bias current of 223uA. I'm guessing Neumann selected 225uA which is really close.
With the drain bias and drain resistor selected, we need to figure out the idling point next. I'll spare the detailed math, but you essentially look at the VGS / IDS transfer curve, and find a point roughly around the point that intersects 225uA. I've found for the nominal 2N3819, this voltage is roughly -3.4V (but given JFET parameter swing, can be anyplace from -0.2V up to damn near -7V!). If you measure the IDSS and IDS points you can calculate VP, then use the equations I provided earlier to find the VGS that intersects with the 225uA point with a spreadsheet.
So if the nominal 2N3819 has a VGS at -3.4V at a quiescent current of 225uA, then the source resistor needs to be 15.2K. This will place the source voltage at 3.4V. With a 47K drain resistor, the drain will idle at 10.5V given these nominal JFET conditions, which I have confirmed with a SPICE simulation.
Herein lies the first problem with this circuit: in order to be in the saturation region, the VDS voltage must be held above VP, otherwise the JFET is operating in it's ohmic (or triode) region. In this region, the drain->source current starts to depend on VDS (and not just on VGS). As the VDS falls, the transistor impedance rises, which can be thought of as a "softening" of the pulling ability of the JFET down towards it's source terminal (it essentially becomes a VCR, or "voltage controlled resistor").
In any case, we must maintain VDS at greater than VP (which in this case is 4V for the nominal 2N3819). Now while the trouble is on the downward slope for output (meaning on the upward slope on the input, given this is an inverting stage), due to the action of gm against RD, the drain voltage will fall "faster" than the source voltage. If this difference falls below VP, the waveform will start suffering a lot of THD.
You can see this for the nominal U87 circuit with a nominal JFET in the SPICE plot below:
which is a plot of VDS with an input signal of 1kHz, 200mV peak to peak. You can see that as the output signal falls below the 4V threshold, the signal flattens out.
This means that the VP level greatly reduces the amount of gain we can realize while still maintaining low distortion. Although the gain calculates at roughly 35, we can really only make use of the first 88mV of input signal before the stage begins to run out of signal swing headroom.
There are two ways this can be mitigated: the first is to run higher quiescent current. This has the effect of reducing the VGS bias, which means that the source resistor can be smaller. With less VGS bias, we can swing more signal. This has the secondary effect of reducing gain however, but we do get more input headroom.
The other way is to jack up the VDD voltage from 21V. For example, if we raise this up to 30V, and idle at 15V, then we can raise up the drain resistor to 67K and have a few more volts of headroom before we start to run into trouble. We have to be careful however, as if we exceed the maximum drain to gate voltage (25V for the 2N3819) we get into more trouble. 30V is about as high as one can go.
Here is the same plot with 30V VDD, 15V idle:
Looks much cleaner, gain is slightly higher as well (50 versus 35, with a larger input swing too). Output impedance is higher however, which means we have to think about dampening into the output transformer too!
The fundamental problem here is that with a nominal JFET, we are operating too far away from IDSS. With IDSS also comes lower VP, which means less headroom.
Here is the same idea with a minimal JFET (2mA IDSS, VP of -0.22V). Gain is up another full order of magnitude (around 100), and we have tons more output swing to use up because VGS is so low (about -0.15V). Gain is up because we are so much closer to IDSS in the quiescent state. The simulation shows that 30mV at the input swings nearly 7V at the output.
However input headroom is tiny: roughly 50mV will take the output to the rail. This may be ok if you are only room miking at a distance, but this would distort heavily on loud sources I am guessing.
What I'll do next is post a chart of IDSS and VP, and what the gain and headroom look like. That way, you can hand select a JFET to go with whatever operation you like. I'll also post the source resistor values so that those without a scope can get very close to the ideal value.
Marcocet
Well-known member
Thanks Matador! You have once again significantly increased my understanding of a circuit.
kante1603
Well-known member
Same here,thank you so much matador for your deep and well documented investigations!Marcocet said:
Interesting how complex this little fet circuit can be and to see (and learn in my case) what it is doing under different circumstances.I'm really curious now what the results may be with a minimal fet at low Idsss.
Cheers,
Udo.
dissonantstring
Well-known member
thank you matador! your explanation is so well prepared and makes things so understandable. one of the best tutorials i've seen here that is so project specific and yet yields such a great amount of knowledge as well about JFETs. looking forward to your next installment.
kindest regards,
grant
kindest regards,
grant
Matador
Well-known member
Thanks for all the kind words!
I created a simple PHP script to do all the calculations for everyone. It's located here:
http://www.musicalsparks.com/images/curve_tracer/jfet_bias.php
You plug in the two values that you measure for your JFET, and it will do all of the math and tell you the values of all the resistors, the gain, and calculate the maximum input signal before clipping. If you have a handful of JFET's (even different types), you can plug in the data and see what it gives.
For example, if I use my nominal JFET that I have (IDSS = 10.79mA, VGS at 1% IDSS = -3.4V), this is what is spit out:
VP = -3.77777777778 V
gmo = 5712.35294118 µmho
β = 0.756046712803m
VDD = 21 V
VD = 10.5 V
IDQ = 225 µA
RD = 46.6666666667 kΩ
VGSQ = -3.23224990585 V
RS = 14.3655551371 kΩ
gm = 824.889108622 µmho
AV (gain) = 38.494825069
Headroom Analysis
Output swing headroom (positive) = 10.5 V
IDO (ohmic) ≤ 282.182455648 µA
Output swing headroom (negative) = 6.72222222222 V
Maximum input signal before clipping = 174.626646833 mV
For those of you without a scope and only a simple DVM, this calculation for the source resistance should be VERY close to the optimal value for that JFET.
I went through most of my stash of 2N3819's and have a few near the extremes of the ranges. I'll breadboard up the circuit and inject a test signal and we'll see how close the math is to reality.
I created a simple PHP script to do all the calculations for everyone. It's located here:
http://www.musicalsparks.com/images/curve_tracer/jfet_bias.php
You plug in the two values that you measure for your JFET, and it will do all of the math and tell you the values of all the resistors, the gain, and calculate the maximum input signal before clipping. If you have a handful of JFET's (even different types), you can plug in the data and see what it gives.
For example, if I use my nominal JFET that I have (IDSS = 10.79mA, VGS at 1% IDSS = -3.4V), this is what is spit out:
VP = -3.77777777778 V
gmo = 5712.35294118 µmho
β = 0.756046712803m
VDD = 21 V
VD = 10.5 V
IDQ = 225 µA
RD = 46.6666666667 kΩ
VGSQ = -3.23224990585 V
RS = 14.3655551371 kΩ
gm = 824.889108622 µmho
AV (gain) = 38.494825069
Headroom Analysis
Output swing headroom (positive) = 10.5 V
IDO (ohmic) ≤ 282.182455648 µA
Output swing headroom (negative) = 6.72222222222 V
Maximum input signal before clipping = 174.626646833 mV
For those of you without a scope and only a simple DVM, this calculation for the source resistance should be VERY close to the optimal value for that JFET.
I went through most of my stash of 2N3819's and have a few near the extremes of the ranges. I'll breadboard up the circuit and inject a test signal and we'll see how close the math is to reality.
wave
Well-known member
Matador,
You rock! This will help me out as I don't have a scope yet and I do the listen method which is hard in it's own right.
Thanks!
Dave
You rock! This will help me out as I don't have a scope yet and I do the listen method which is hard in it's own right.
Thanks!
Dave
Similar threads
