I've been working on this again and made some findings. The circuit runs stable in prototype within a range of 50Hz to 14.5kHz (BW 0.082-2.24oct, Gain 27dB), basically full-range.
Can't credit myself, since it is directly based on
@JohnRoberts and
@abbey road d enfer suggestions in posts
#53 and
#57, who proposed to place a large resistor between the output of the summing amplifier and the -IN of the first integer opamp. The suggestion was to improve the pot tolerance at low freqs, but incidentally it allows a wider range by removing the resistor from the freq pots to ground. Instead of the 68k resistor suggested I used a 100k to increase the range even more.
The key to stability seems to be grounding the fpots straight to VGND instead of GND. Any capacitor between the fpots and GND or VGND will make the circuit oscillate (even in simulation it seems!).
The only problem I've encountered recently is scratchiness when changing frequency.
@JohnRoberts warned me about this before, but wasn't clear on how to solve it. I'm using the OPA1642 now, which has very low noise current, perfect for those big 20k resistors setting bandwidth, but offset voltage is not the best. Since a coupling capacitor to GND or VGND produces oscillation, I'm planning to couple the wiper of the freq pots instead, which seems to work fine in sim. But I'm not sure if 10u is a good value, neither have I tried it yet. I thought it was wise to publish this progress and ask here before putting back my fingers on it.
Please, all comments on the overall design are more than welcome. Especially regarding the fpots wiper coupling capacitors (C4, C5) just mentioned.
Thanks for all the comments here and the knowledgeable masters for your contributions!
Domingo