Sorry I didn't mean to hijack this thread or turn it into a tutorial on side chain design but let me back up a little and fill in some gaps.
First, yes that looks like an huge improvement in driving the VCA with a cleaner and lower impedance drive. To maintain stereo linking you need to connect your sidechain/link node to the + input of the opamp so they will sum resistively. It's worth note that doing so will result in a 50:50 contribution from each channel. With some additional opamp tricks you could make both track the most de-essed of both channels but not tonight.
OK back to sidechains and opamps 101. The main issue is dealing with control voltages on the order of a 6 mV/dB with opamps so that the opamp's noise and dc offsets don't cause errors. The 5532 and TL074 are both old soldiers and old favorites of mine from a back in the day.
Door #1 TL074
++ high input impedance
++ low/no bias current due to FET input
++ fast (13 V/usec)
+ moderately low noise (approx 3 uV)
- wimpy drive capability (approx 2k)
-- poor DC offsets (as bad as 15mV for some grades)
Door #2 5532
++ low noise (approx .5 uV)
++ fast (10 V/usec)
++ good drive capability (approx 500 ohms)
++ good DC offset (perhaps < 1 mV)
- bipolar input impedance (lower than FET opamp)
- bipoloar input bias and offset current
Finally an observation about the THAT (dBx) RMS chip. I haven't looked inside to see if there's ways to game it, but it looks like it's designed to work in minimum part configuration comp/NR or whatever. Full scale voltage is on the order of 300 mV with limited drive capability (looks like 2K but data sheet describes out specific limits as some multiple of bias current).
With out mapping out a full proof, I see two alternate approaches using those part choices. To use TL074 you want to scale up the CV at least 10x to make bifet opamp noise and offset voltages insignificant. Alternately using the 5532 the noise and DC offset voltages are not problematic, but DC errors due to bipolar input bias and offset currents can introduce errors depending on resistor values and matching so play is just keep impedances low with stepping up.
Another consideration mitigating against scaling up the control voltage for bifet is the one time scaling of the DC also multiplies the offset voltage of that ifrst opamp stage, With only one offset trim for two RMS detectors trimming both is not judicious (in fact I don't like trims at all from years of design for production).
So that said and guessing you are perhaps looking for specific advice more than a professorial lecture, I would be inclined to stay with the 5532s and not scale up the 300mV.
Note: The roughly 3x in the initial design at that intermediate stage was not for DC accuracy but to provide the following stage with a useful compliance for the shunt FET to work into, and for stereo linking(?). Pushing it up 10x, and then down again in the very next stage buys little to nothing.
Back to specifics. Since the 2252 will drive 2k (I think I saw that in app notes) , using that lower impedance will reduce noise and bias current errors in 5532 unity gain inverter. Note: the resistor from + pin to ground is needed with 5532 and should be 1k (2k feedback in parallel with 2k input).
For the 5532 at the final sum/calculation amp the input bias correction is not clear cut due to diode steering and following configuration. Since the sources coming in are already corrected to zero, I would connect the + pin directly to 0V with no resistor and use the offset trimpot to correct for that, and all other errors.
For the feedback resistor at that stage something like 3x is OK but since that is not a round value with 5% resistors I'll leave that to you to figure out something specific in that range and following divider. With the bipolar opamps you might want to keep impedances of following divider a little lower, but this has to be traded off against shunt capability of JFET.
Correcting the bias current related DC errors at buffer 5532 is rather conflicted also since the DC impedance at the - input is now well defined (1k), but the DC impedance at the + input varies depending on the state of the FET shunt and whether diodes are forward or reverse biased in operation.
Again I'm inclined to just let the offset trim this out. but it can only be trimmed completely for one mode.
I hope this is making some sense and I'm not making this sound too mysterious. The old opamps required a little more math to get good results. The modern hot stuff opamps don't have bias current errors, and do have low offset and low noise... but they cost more $$ than the old soldiers.
Good luck
JR
First, yes that looks like an huge improvement in driving the VCA with a cleaner and lower impedance drive. To maintain stereo linking you need to connect your sidechain/link node to the + input of the opamp so they will sum resistively. It's worth note that doing so will result in a 50:50 contribution from each channel. With some additional opamp tricks you could make both track the most de-essed of both channels but not tonight.
OK back to sidechains and opamps 101. The main issue is dealing with control voltages on the order of a 6 mV/dB with opamps so that the opamp's noise and dc offsets don't cause errors. The 5532 and TL074 are both old soldiers and old favorites of mine from a back in the day.
Door #1 TL074
++ high input impedance
++ low/no bias current due to FET input
++ fast (13 V/usec)
+ moderately low noise (approx 3 uV)
- wimpy drive capability (approx 2k)
-- poor DC offsets (as bad as 15mV for some grades)
Door #2 5532
++ low noise (approx .5 uV)
++ fast (10 V/usec)
++ good drive capability (approx 500 ohms)
++ good DC offset (perhaps < 1 mV)
- bipolar input impedance (lower than FET opamp)
- bipoloar input bias and offset current
Finally an observation about the THAT (dBx) RMS chip. I haven't looked inside to see if there's ways to game it, but it looks like it's designed to work in minimum part configuration comp/NR or whatever. Full scale voltage is on the order of 300 mV with limited drive capability (looks like 2K but data sheet describes out specific limits as some multiple of bias current).
With out mapping out a full proof, I see two alternate approaches using those part choices. To use TL074 you want to scale up the CV at least 10x to make bifet opamp noise and offset voltages insignificant. Alternately using the 5532 the noise and DC offset voltages are not problematic, but DC errors due to bipolar input bias and offset currents can introduce errors depending on resistor values and matching so play is just keep impedances low with stepping up.
Another consideration mitigating against scaling up the control voltage for bifet is the one time scaling of the DC also multiplies the offset voltage of that ifrst opamp stage, With only one offset trim for two RMS detectors trimming both is not judicious (in fact I don't like trims at all from years of design for production).
So that said and guessing you are perhaps looking for specific advice more than a professorial lecture, I would be inclined to stay with the 5532s and not scale up the 300mV.
Note: The roughly 3x in the initial design at that intermediate stage was not for DC accuracy but to provide the following stage with a useful compliance for the shunt FET to work into, and for stereo linking(?). Pushing it up 10x, and then down again in the very next stage buys little to nothing.
Back to specifics. Since the 2252 will drive 2k (I think I saw that in app notes) , using that lower impedance will reduce noise and bias current errors in 5532 unity gain inverter. Note: the resistor from + pin to ground is needed with 5532 and should be 1k (2k feedback in parallel with 2k input).
For the 5532 at the final sum/calculation amp the input bias correction is not clear cut due to diode steering and following configuration. Since the sources coming in are already corrected to zero, I would connect the + pin directly to 0V with no resistor and use the offset trimpot to correct for that, and all other errors.
For the feedback resistor at that stage something like 3x is OK but since that is not a round value with 5% resistors I'll leave that to you to figure out something specific in that range and following divider. With the bipolar opamps you might want to keep impedances of following divider a little lower, but this has to be traded off against shunt capability of JFET.
Correcting the bias current related DC errors at buffer 5532 is rather conflicted also since the DC impedance at the - input is now well defined (1k), but the DC impedance at the + input varies depending on the state of the FET shunt and whether diodes are forward or reverse biased in operation.
Again I'm inclined to just let the offset trim this out. but it can only be trimmed completely for one mode.
I hope this is making some sense and I'm not making this sound too mysterious. The old opamps required a little more math to get good results. The modern hot stuff opamps don't have bias current errors, and do have low offset and low noise... but they cost more $$ than the old soldiers.
Good luck
JR