I am building an Alice style circuit (designed myself) based heavily on the "Pimped Alice" circuit found here. I have got it "working" with a JLI2555 electret capsule but there is a significant noise floor (audibly). Vcc is about 11.3V so I am trying to bias the 24116A to ~2.75V. I have tried resistances in the range of 1k to 8.2k and haven't been able to reach above 2.1V at source. My understanding of analog electronics is lacking so I could be missing a key concept of JFET operation. I measured a voltage of about 10V at the drain which made me think the drain resistor was improperly selected. I tried changing it to 8.2k giving me a drain voltage of about 8.5V which seems closer to 3/4 of Vcc given that it's a differential amp. I find it hard to believe that the circuit design is the mistake as it's a proven design and I must have made a mistake somewhere so if anyone can point me in the right direction it would be much appreciated. The capsule is connected for these tests which could be a mistake but I didn't think it was.
Help biasing Alice JFET
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oscarhuang
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I'm also waiting for an answer. But I think the voltage of TP1 should be a quarter of TP2. I don't know if it's right or not.
I could be misguided but my understanding of a single ended amp is that you would want to bias the jfet at half rail for get maximum headroom. Since this is double ended my understanding is you would want the drain and source equally distributed between rail and gnd therefore giving .75Vcc at drain and .25Vcc at source. Hopefully someone more experienced can confirm whether that's correct or not.
oscarhuang
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I have a stellar x2 mic. TP1 is 2v. TP2 is around 8v.
The schematics show Q2 connected backwards (you swapped emitter and collector), that will screw up the power supply and the hot leg output. That could be part of the cause of low signal level (although I am making a leap and assuming that part of your audible hiss complaint is because the signal level is low and you are turning up your mic amp gain to compensate).
Does that mean getting gate to source voltage of 2.75V? You mention the drain voltage, but not the source voltage, and for a JFET the gate-to-source voltage is what controls biasing.
Your schematic says 2N4416A, which has a minimum off voltage of 2.5V. Maybe your JFET is on the low end of the range (VGS(off) between 2.5V min and 6V max, at least for the Central Semi version of the part), and the current is really low at the Vgs you have.
Did you actually use a 2N4416A, or did you use a 2N4416? The non-"A" version of the part has an even wider variation in VGS(off). The datasheet doesn't guarantee a minimum value, but they have curves plotted for VGS(off) of 1.2V.
The design you linked in your post shows a PF5102 JFET, which has a 0.7 to 1.6V cutoff voltage, quite a bit lower range than the 2N4416 you show in your schematic.
And now that I look more closely, you wrote "24116A" which isn't an actual part number. If you mean 2N4116, that is a bipolar transistor and won't work at all in place of a 2N4416A, which is an N channel JFET.
So I guess the first step is to verify what part you actually put in your circuit, a 2N4116, a 2N4416A, a 2N4416, or something altogether different.
That is the classic Schoep style circuit, I'm pretty sure that you have to test and select the JFET for a narrow range of VGS(off) and IDSS values for the biasing to work out with fixed resistor values for the drain and source resistors. You may have to build a test fixture and verify the I vs. VGS curve for the specific JFET you have in hand to pick appropriate resistor values. Assuming it actually is a JFET, and you didn't order a 2N4116 by mistake.
Does that mean getting gate to source voltage of 2.75V? You mention the drain voltage, but not the source voltage, and for a JFET the gate-to-source voltage is what controls biasing.
Your schematic says 2N4416A, which has a minimum off voltage of 2.5V. Maybe your JFET is on the low end of the range (VGS(off) between 2.5V min and 6V max, at least for the Central Semi version of the part), and the current is really low at the Vgs you have.
Did you actually use a 2N4416A, or did you use a 2N4416? The non-"A" version of the part has an even wider variation in VGS(off). The datasheet doesn't guarantee a minimum value, but they have curves plotted for VGS(off) of 1.2V.
The design you linked in your post shows a PF5102 JFET, which has a 0.7 to 1.6V cutoff voltage, quite a bit lower range than the 2N4416 you show in your schematic.
And now that I look more closely, you wrote "24116A" which isn't an actual part number. If you mean 2N4116, that is a bipolar transistor and won't work at all in place of a 2N4416A, which is an N channel JFET.
So I guess the first step is to verify what part you actually put in your circuit, a 2N4116, a 2N4416A, a 2N4416, or something altogether different.
That is the classic Schoep style circuit, I'm pretty sure that you have to test and select the JFET for a narrow range of VGS(off) and IDSS values for the biasing to work out with fixed resistor values for the drain and source resistors. You may have to build a test fixture and verify the I vs. VGS curve for the specific JFET you have in hand to pick appropriate resistor values. Assuming it actually is a JFET, and you didn't order a 2N4116 by mistake.
Thank you so much for your detailed reply. I have confirmed that I ordered the 2N4416A per my mouser order 
I will be fixing the orientation of q2 as that’s clearly a problem. I have my preamp set to about 50% which I know is a bit arbitrary (scarlet solo) but compared to the default Chinese bm700 I’m getting about the same signal level.
My first step will be fixing the pnp orientation and will revisit the biasing. But to clear up confusion my Vcc is about 11.3V, JFET Drain is about 10V with 2.2k resistor and JFET source is about 1.7V with 2.2k resistor. I was trying to target 2.8V at the JFET source for proper biasing and tried various values but wasn’t able to achieve more than 2.1V but maybe this is because of the PNP.
I have to admit I’m struggling a bit to properly understand the biasing process of the JFET so any explanation you can give or point me towards any good resource would be appreciated.
I will look more into how to test the I/Vgs of the jfet as I must admit I’m a bit lost.
I will be fixing the orientation of q2 as that’s clearly a problem. I have my preamp set to about 50% which I know is a bit arbitrary (scarlet solo) but compared to the default Chinese bm700 I’m getting about the same signal level.
My first step will be fixing the pnp orientation and will revisit the biasing. But to clear up confusion my Vcc is about 11.3V, JFET Drain is about 10V with 2.2k resistor and JFET source is about 1.7V with 2.2k resistor. I was trying to target 2.8V at the JFET source for proper biasing and tried various values but wasn’t able to achieve more than 2.1V but maybe this is because of the PNP.
I have to admit I’m struggling a bit to properly understand the biasing process of the JFET so any explanation you can give or point me towards any good resource would be appreciated.
I will look more into how to test the I/Vgs of the jfet as I must admit I’m a bit lost.
That's a good question. My understanding is that "proper biasing" can vary based on maximising for headroom or for harmonic distortion. Following the original circuit I linked by Homero it is suggested to aim for 1/4Vcc at JFET source which would theoretically give maximum headroom of the differential output before any clipping. What confuses me in this case (and it could all be down to my mistake of the PNP orientation) is that I wasn't able to freely manipulate Vsource. My concern is partially performance based as well as learning from an analogue electronics standpoint. I could be way off so if I've made a mistake or misunderstood I'm more than happy to be corrected. This is my first foray into building microphones.
Since JFET parameters have humongous tolerances, aiming for an arbitrary voltage is merely a starting point, or a ballpark-figure.
If anything, the "roughly mid-supply" holds true for most of these single-ended circuits (even if we're also tapping off a signal from the source pin), so i wouldn't worry too much.
If you really want to "guild the lily", disconnect the capsule and hook up a test-signal sinewave to the JFET gate, and monitor the mic output with either REW, or your favorite DAW and an oscilloscope plugin and/or an FFT spectrum analyzer.
In the original circuit, the 1Gohm resistor coming from the gate is connected to the wiper of a 1meg trimpot that's in parallel with the source resistor (google for "Schoeps schematic). That gets tweaked for either max headroom or minimum distortion. @RuudNL has done more testing on that, and has concluded you can't achieve both at the same time.
If anything, the "roughly mid-supply" holds true for most of these single-ended circuits (even if we're also tapping off a signal from the source pin), so i wouldn't worry too much.
If you really want to "guild the lily", disconnect the capsule and hook up a test-signal sinewave to the JFET gate, and monitor the mic output with either REW, or your favorite DAW and an oscilloscope plugin and/or an FFT spectrum analyzer.
In the original circuit, the 1Gohm resistor coming from the gate is connected to the wiper of a 1meg trimpot that's in parallel with the source resistor (google for "Schoeps schematic). That gets tweaked for either max headroom or minimum distortion. @RuudNL has done more testing on that, and has concluded you can't achieve both at the same time.
That makes sense. I would like to try what you suggested but don't have a clean sinewave. Where does the suggestion of 1/4Vcc come from as it seems as though I'm way off with 1.7V and 11.3V supply. It's slowly starting to click but I think I'm still confused on it being single-ended vs differential.
Yes you do. Just play a sinewave from your computer. Your sound interface output will have orders of magnitude lower distortion than the mic input. You can't go by voltages because the point at which you get proper bias point is so tiny, your DMM probably can't measure that precisely.
https://groupdiy.com/threads/schoeps-cmc5-inductor-values.73321/
If you look at the original Schoeps schematic, which the Alice is a 98% clone of, you'll see the JFET is supplied with about 6.2v, and the drain voltage is roughly* 4.5v.
* Roughly = may or may not end up there, depending on what JFET you use, and where it ends up needing to be biased, for best results (greatest headroom or lowest distortion, as pointed out above)
If you look at the original Schoeps schematic, which the Alice is a 98% clone of, you'll see the JFET is supplied with about 6.2v, and the drain voltage is roughly* 4.5v.
* Roughly = may or may not end up there, depending on what JFET you use, and where it ends up needing to be biased, for best results (greatest headroom or lowest distortion, as pointed out above)
Something is off there just a little, your numbers would imply 0.59mA through the drain resistor, and 0.77mA through the source resistor.
I don't see any other DC paths, so I will assume that is just measurement error. If it is not just measurement error then that implies another DC current path somewhere which is not indicated in your schematics (or the resistor values are incorrect).
The source voltage is determined by the current through the source resistor (I*R). Since the gate is fixed at 0V, the voltage at the source sets the gate-source voltage (which is usually actually measured as the source-gate voltage, reference/negative terminal of your volt meter connected to the source terminal, i.e. 1.7V at the source and 0V at the gate would be referred to as -1.7V since the gate is more negative than the source).
You could increase the R term in the V=IR equation, but that will increase the difference in gate to source voltage, which will bias the JFET closer to cutoff, i.e. less current, which will decrease V.
I am referencing the Central Semi datasheet here:
Central Semi 2N4416 datasheet
Note in the electrical characteristics table on the first page that VGS(off) is listed as between 2.5V and 6.0V.
You have a measured drain-source voltage of 8.3V (with the caveat noted above that the values given are not physically possible exactly as described) and a gate to source voltage of 1.7V.
Looking on the electrical characteristics graphs on page 3 you can see in the top left graph that if the device has a VGS(off) value of 5V, then at 8V Vds and 1.7V Vgs the current would be about 7mA. 7mA across 2.2k Ohms would be 15V, so you know that does not match the device in your circuit.
The graph below that for a device with Vgs(off) of 1.2V would have 1.7V gate to source voltage off the graph to the bottom, since 1.7V is more than the cutoff voltage of a Vgs(off)=1.2V device (cutoff in that datasheet is defined as the voltage which causes device current to drop to 1nA).
You can hopefully see from the wildly different y-axis labels on those two graphs that it would be nearly impossible to have circuit components which give a specific voltage for any randomly picked 2N4416 device (since the same gate voltage could result in anywhere from under 1mA to over 10mA).
To get your circuit to work you either have to buy a large number of devices, and measure them all until you find one with the Vgs to current relationship you want, or you have to change the circuit so that the gate voltage can be adjusted to match the specific device you have.
Thank you so much for the comprehensive response. As mentioned above I did indeed have a reversed PNP (Q2) which turned out to be the cause of the noise. Fixing that cleaned it right up and I'm quite happy now with the performance of the mic. I will try using REW to generate a tone and measure the response of the microphone and see if I can improve the bias point.
After fixing the orientation of the transistor I briefly re-measured drain and source voltage and got: Vcc = 11.3, Drain = ~8.1 and source = 1.7V. This still seems strange as if I understood correctly I should have about 1.45mA through the drain resistor and .77mA through the source resistor. I will turn it on and let it settle a bit and re-measure because I'm also a bit lost on what's going on with that.
After fixing the orientation of the transistor I briefly re-measured drain and source voltage and got: Vcc = 11.3, Drain = ~8.1 and source = 1.7V. This still seems strange as if I understood correctly I should have about 1.45mA through the drain resistor and .77mA through the source resistor. I will turn it on and let it settle a bit and re-measure because I'm also a bit lost on what's going on with that.
Screw the currents, and screw the source pin voltage. Still no idea why exactly you're so hung up on the latter.
REW measurements and biasing will show you where the bias needs to be. Forget whatever voltages you measure, they're nearly / virtually guaranteed to NOT be the same for the next JFET you use.
REW measurements and biasing will show you where the bias needs to be. Forget whatever voltages you measure, they're nearly / virtually guaranteed to NOT be the same for the next JFET you use.
Maybe I should have been clearer. I have understood that purely measuring voltages or current is not the way to bias the JFET. In my previous comment I mentioned the voltages again because ccaudle rightly suggested it was incorrect/impossible (seems due to the inverted PNP). I am both trying to get the best sounding mic I can with this build as wel as LEARN. I asked a few times why no matter what resistance I set on source I could not manipulate the source voltage to be above 2.1V fully aware that it could be the wrong thing to do but wanting to understand this weird (to me) behavior. I did state that I will be using REW to properly bias the JFET but it doesn't mean it's not helpful and interesting to me to learn about the theory of the JFET design. Not trying to ignore your helpful suggestions or comments but I'm also responding to other people that have also suggested things to consider.
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