Help biasing Alice JFET

[aggo]

It's going straight to ground per the scott helmke alice design. I have seen some topologies that feed the 1G resistor through a trimpot to the source. Is it a mistake on my part or just a different way of going about it?

 

[Khron]

Different in the sense that it technically doesn't allow for biasing, as such. Or at least i don't necessarily consider swapping out umpteen passive components until you get it "just right", as biasing.

In the original circuit, the 1Gohm resistor coming from the gate is connected to the wiper of a 1meg trimpot that's in parallel with the source resistor (google for "Schoeps schematic). That gets tweaked for either max headroom or minimum distortion. @RuudNL has done more testing on that, and has concluded you can't achieve both at the same time.

https://groupdiy.com/threads/schoeps-cmc5-inductor-values.73321/

 

[aggo]

So in order to bias it I replaced the source resistor with ~8.2k and added a 1M (what I had on hand) trimpot to adjust the source resistance. Not just arbitrarily swapping out resistors. But there seems to be a meaningful difference in connecting the 1G resistor to source rather than to ground which I don't understand.

 

[Khron]

https://en.m.wikipedia.org/wiki/JFET

When the depletion layer spans the width of the conduction channel, pinch-off is achieved and drain-to-source conduction stops. Pinch-off occurs at a particular reverse bias (VGS) of the gate–source junction. The pinch-off voltage (Vp) (also known as threshold voltage[7][8] or cut-off voltage[9][10][11]) varies considerably, even among devices of the same type. For example, VGS(off) for the Temic J202 device varies from −0.8 V to −4 V.[12] Typical values vary from −0.3 V to −10 V. (Confusingly, the term pinch-off voltage is also used to refer to the VDS value that separates the linear and saturation regions.[10][11])

To switch off an n-channel device requires a negative gate–source voltage (VGS). Conversely, to switch off a p-channel device requires positive VGS.

That's what the trimpot in the original Schoeps circuit does - it shifts the DC voltage that the JFET gate is biased at, relative to the voltage at the source pin. Sure, there will be a bit of interaction while turning the trimpot (the higher JFET gate voltage, the lower the source voltage will be, and vice-versa), but if you monitor the spectrum in real time (like with REW's RTA function), you'll see the harmonics of your test signal increase or decrease, as you bias the JFET closer to or further from the Goldilocks area.

If the negative voltage thing is confusing, keep in mind that currently, the gate is held at ground (0v), while the source is positive (1.7v or whatever), so the gate-to-source voltage (ie. red probe on gate, black probe on source) is -1.7v, since the gate is at a lower potential / voltage than the source, but the JFET still conducts / amplifies.

 

[aggo]

I think I'll need to sit and think about it for a while. Thanks for taking the time to explain. If you change the source resistance you would change the source voltage and therefore Vgs as the base will stay at 0V. Alternatively if you connect the 1G resistor to source through a trimpot can adjust the base voltage (and therefore Vgs) without changing the source voltage. If I understood that correctly my next question is what is the practical effect/advantage of one way over the other?

 

[Khron]

Vgs (Voltage between Gate and Source) WILL change. The gate is held at 0v, but by changing the source resistance you're changing both the Vgs AND the operating current of the JFET (remember your Ohm's law). That, and throwing the output impedances even more out of balance than they already are in the stock design (with potential consequences affecting CMRR / interference immunity).

 

[aggo]

I think we're saying the same thing. I said that because the source resistance therefore voltage is changing and the base is staying at 0V Vgs is adjusted. I might be misunderstanding your comment but what is the practical difference with one method of bias vs the other. In the second option of connecting the trimpot between the 1G resistor and source you're effectively increasing the base voltage right? Or is the base still held at 0V?

 

[Khron]

Disclaimer: This is only a simulation, and meant only as a comparison between different biasing options. We're at the mercy of the (in)accuracy of existing semiconductor models, and I haven't bothered tweaking things too-too much, just iterated a few resistor values to get just-about-the-lowest-THD with a 200mVpp (100mV peak) input signal.



Below each schematic you'll find the most essential(?) readings. "Vdrain" is the AC amplitude of the signal, "Vd" is the DC point the drain sits at, at idle. Haven't bothered checking the headroom (ie. how much i'd need to increase the input in circuits 1 and 3, to get to the THD of circuit 2, for example), but i'll leave that exercise to you. Just draw the circuit once, copy it over and change whatever needs changing.

 

[kingkorg]

Maybe I should have been clearer. I have understood that purely measuring voltages or current is not the way to bias the JFET. In my previous comment I mentioned the voltages again because ccaudle rightly suggested it was incorrect/impossible (seems due to the inverted PNP). I am both trying to get the best sounding mic I can with this build as wel as LEARN. I asked a few times why no matter what resistance I set on source I could not manipulate the source voltage to be above 2.1V fully aware that it could be the wrong thing to do but wanting to understand this weird (to me) behavior. I did state that I will be using REW to properly bias the JFET but it doesn't mean it's not helpful and interesting to me to learn about the theory of the JFET design. Not trying to ignore your helpful suggestions or comments but I'm also responding to other people that have also suggested things to consider.

https://sound-au.com/articles/jfet-design.htm

 

[ccaudle]

Alternatively if you connect the 1G resistor to source through a trimpot can adjust the base voltage (and therefore Vgs) without changing the source voltage.

If you change the base voltage that is going to change the current through the JFET, which will change the source voltage. They are not independent.

In the second option of connecting the trimpot between the 1G resistor and source you're effectively increasing the base voltage right? Or is the base still held at 0V?

With a trim pot between source and ground, and the gate resistor tied to the wiper, you have made a voltage divider between source voltage and ground.
Not only is the gate not held at 0V, it is not held at a constant DC voltage, it is a proportion of the source voltage. That allows you adjustment room, all the way up to Vgs=0 (i.e. gate resistor is connected directly to the source when the pot is set all the way to one end).

If you do not have any good textbooks available which include a section on JFET devices that link from kingkorg is a good place to start.

 

[ccaudle]

I like this part of that Elliot Sound article:
"One of the reasons for this is that it's so hard to actually design a stage using a JFET, because all of the parameters are so variable. You can perform all the theory you like, examine the graphs in the datasheet until you're bored or bewildered, design the stage based on the theory you just applied, and find it doesn't work. Not because of anything you did, but simply because the wide variation of VGS(off) (in particular) makes most calculations pointless."

 

[aggo]

Thanks everyone for the explanations. I have a lot to learn and wrap my head around so I'm sorry if I came across as argumentative. Those simulations are very helpful I'll just have to go through everything a few times for it to really sink in. That source looks very comprehensive so I'll read through that. I've struggled with basic explanations of how a JFET works but with not enough detail of practical use cases from most websites. Thanks again to everyone I'll be back with a better understanding next time.

 

[aggo]

Small update. I've got some results from REW by outputing the audio signal to the 1G resistor (disconnecting the capsule) and taking the mic output from the audio interface. I have tried adjusting the source resistor although the pot I have is 1M so it's not ideal using it in parallel with the source resistor to ground. At this stage I just want to know any tips or what specifically to look for. My assumption is that I'm biasing for THD+N and it would be nice to know what is an ideal input voltage or a safe one. I need to get some better pots to properly adjust I just want a better understanding of what I'm looking for. Image quality is super average but just as an indication of what the software setup is.

 

[k brown]

Slightly off topic - when loaded with constant-currrent sources as in this design, are the FETs sort of self-biasing in a way, if the two FETs' IDSSs are well-matched?

 

[abbey road d enfer]

. If I understood that correctly my next question is what is the practical effect/advantage of one way over the other?

In addition to the already mentioned ease of trimming the operating point, it allows some FET's with very low Vgsoff, which would otherwise result in very low source voltage, to operate correctly.
For example, LSK489A, with Vfsoff=1.8V, the source voltage cannot go above 1.2V with the common source resistor values.
That shouldn't be a big issue with a standard common-source stage, because the lowest the source voltage, the higher the possible voltage swing for the drain, but in the case of the Schoeps input stage, headroom is directly governed by the operating source voltage.
Using the additional trimmer would allow using all variations of LSK489, with nominal Vgsoff varying from 1.8 to 2.7V.
Makes total sense for a manufacturer, that doesn't want its production halted because its favorite flavout of FET is momentarily unavailable.

 

[Khron]

I have tried adjusting the source resistor although the pot I have is 1M so it's not ideal using it in parallel with the source resistor to ground.

Why??? That description, unless i'm horribly misunderstanding it, is totally not what i tried to get across.

How exactly is that 1M pot connected in your circuit?

 

[abbey road d enfer]

 

[Khron]

That was my exact point; doodling on my phone is not my forte, so i was going to do that on the computer, but @abbey road d enfer - thanks for doing it

 

[abbey road d enfer]

Slightly off topic - when loaded with constant-currrent sources as in this design, are the FETs sort of self-biasing in a way, if the two FETs' IDSSs are well-matched?

Definitely, within limits of course (pentode region).

 

[aggo]

That was my exact point; doodling on my phone is not my forte, so i was going to do that on the computer, but @abbey road d enfer - thanks for doing it

Thanks for the crayon drawings apparently I needed them. I read all the material linked and still somehow managed to miss that obvious point. Back to the drawing board. However is my signal generator output reasonable and or what would you suggest is an appropriate input range to test for?