[quote author="Samuel Groner"]I've thought quite a bit about adding servos to this topology and I didn't come up with a simple yet convincing solution. The problem is the injection point--the obvious place after the input coupling capacitor is somewhat unhappy as the coupling capacitor will interact with the servo action, potentially producing some low-frequency wobbling.[/quote]
I was planning to use the same injection point that you use on your Design B. It might help to make the injection symmetrical by using an inverting amp to couple into the node connecting R9 and R10; the nice thing about that is that (with sufficient decoupling) the AC impedance of both input legs is even better matched, improving CMRR. I have to test and see how that works out.
The interaction with the input coupling caps is fixable by making the time constant of the servo sufficiently larger than that of Rin*Cin. A factor of 10 is usually enough, in my experience. This may mean that the mic pre needs to settle for half a minute after turning P48 on or off, but I don't care too much (customers might feel differently).
[quote author="Samuel Groner"][quote author="I"]My plan consists of a few DOAs designed to run from +60/-15 supplies, dropped into a standard differential Cohen mic pre, with a few floating servos to preserve DC balance. Plan B would involve a diff-in/diff-out DOA, but I'm not sure if imperfect matching between each output's compensation network might not make an oscillator out of such a beast.[/quote]
If you are interested, I've a presumably nice 80 V DOA in the pipline.[/quote]
Yes, please ! Mine is rather inspired by your DOA as it is, and I'm looking to design a pre not a DOA.
[quote author="Samuel Groner"]For sure I would be curious to see your fully differential opamp![/quote]
It is still very much a work in progress. For a rough idea, take the SGA-SOA, add a collector resistor to Q2, duplicate the gain and output stages (Q4-Q7) to get a negative output, and add a regular op-amp to set the common mode voltage on the output. Will post schematics if I ever get anything that's even marginally stable.
[quote author="JohnRoberts"]Does cap coupling the clock cause actual jitter (an uncertainty from one clock to the next) or some fixed timing error due to C, perhaps interacting with device input C? This is beyond my understanding of things digital I guess but I don't see how a constant timing error from a passive component causes noise, variable timing errors sure.[/quote]
There are two different issues here. First:
[quote author="JohnRoberts"] [...] the last codec I worked with had a PLL that would just hunt and recover (I think... I never actually tried this with one).[/quote]
[quote author="I"]This approach works well, if you/your customers are content with 30..100ps clock jitter[/quote]
This
30..100ps clock jitter is mostly due to the use of PLLs. I know of no integrated audio PLL with typical clock jitter specs much better than 100ps. This is partly because many of them use on-chip ring oscillators or integrated LC VCOs, which have much lower Q than a crystal, and partly because it is hard (read:expensive) to build a phase comparator with a noise figure that is comparable to that of a good XO. If you know of any commercial PLLs which achieve much less than 30ps jitter on a 24.576MHz clock do let me know.
The other thing is:
[quote author="I"]The main stumbling block (as far as I could see) is low-jitter master clock distribution. The best I could think of was transformer coupling of the 24.576MHz MCLK into a low-noise limiting differential amplifier, but even that will easily double the jitter of a good low-noise clock source over impedance-matched DC coupling.
[/quote]
Assuming a good low-noise MCLK has 2.5ps jitter, sinusoid signal shape, 24.576MHz @ 3Vpp (LVCMOS), and the ADC clock input has its threshold exactly at mid-voltage. The slew rate at the switching point is
dV/dt = (2*pi*f*A)
= (2*pi*24.576M*(3V/2))
= 231MV/s = 231uV/ps
A little under 600uV (231*2.5) wideband noise is enough to double the 2.5ps jitter! With the supply servo it's likely that converter and backplane ground will have more noise between them than that, so single-ended capacitor coupling is out. Differential coupling is possible, but most semiconductor differential to single ended converters have a few ps jitter, too. So it's not the capacitors per se that are introducing the jitter, it's the whole clock chain. Some can be gained by using a clipped sine as that speeds up the edge rate, but this introduces harmonics and makes the system sensitive to group delay. RF transformers work best, but even then you'd likely need some narrowband filters on the receiving end to minimize the jitter.
[quote author="JohnRoberts"][quote author="I"][...] dropped into a standard differential Cohen mic pre [...][/quote]
I'm still not sure why Cohen gets credit for that topology.[/quote]
I get the feeling that most people here know of the Cohen design (or the Green pre), so for me it's more a matter of using a commonly understood term than giving credit.
The much earlier version that I first saw (Transamp/Buff) doesn't pass DC offsets to the output so may be preferable for your app.
Do you mean like
the Valley People mic pre (as discussed in
this thread) ? I'll look into it, but I'm not too happy about the large cap/resistor values. I understand that the feedback should cancel most of the badness, but I'm still trying to see how a no-cap pre will sound (just like I want to know what an ADC sounds like when it's fed directly by a transformer).
JDB.