[quote author="jdbakker"]
[quote author="JohnRoberts"]Does cap coupling the clock cause actual jitter (an uncertainty from one clock to the next) or some fixed timing error due to C, perhaps interacting with device input C? This is beyond my understanding of things digital I guess but I don't see how a constant timing error from a passive component causes noise, variable timing errors sure.[/quote]
There are two different issues here. First:
[quote author="JohnRoberts"] [...] the last codec I worked with had a PLL that would just hunt and recover (I think... I never actually tried this with one).[/quote]
[quote author="I"]This approach works well, if you/your customers are content with 30..100ps clock jitter[/quote]
This
30..100ps clock jitter is mostly due to the use of PLLs. I know of no integrated audio PLL with typical clock jitter specs much better than 100ps. This is partly because many of them use on-chip ring oscillators or integrated LC VCOs, which have much lower Q than a crystal, and partly because it is hard (read:expensive) to build a phase comparator with a noise figure that is comparable to that of a good XO. If you know of any commercial PLLs which achieve much less than 30ps jitter on a 24.576MHz clock do let me know.
The other thing is:
[quote author="I"]The main stumbling block (as far as I could see) is low-jitter master clock distribution. The best I could think of was transformer coupling of the 24.576MHz MCLK into a low-noise limiting differential amplifier, but even that will easily double the jitter of a good low-noise clock source over impedance-matched DC coupling.
[/quote]
Assuming a good low-noise MCLK has 2.5ps jitter, sinusoid signal shape, 24.576MHz @ 3Vpp (LVCMOS), and the ADC clock input has its threshold exactly at mid-voltage. The slew rate at the switching point is
dV/dt = (2*pi*f*A)
= (2*pi*24.576M*(3V/2))
= 231MV/s = 231uV/ps
A little under 600uV (231*2.5) wideband noise is enough to double the 2.5ps jitter! With the supply servo it's likely that converter and backplane ground will have more noise between them than that, so single-ended capacitor coupling is out. Differential coupling is possible, but most semiconductor differential to single ended converters have a few ps jitter, too. So it's not the capacitors per se that are introducing the jitter, it's the whole clock chain. Some can be gained by using a clipped sine as that speeds up the edge rate, but this introduces harmonics and makes the system sensitive to group delay. RF transformers work best, but even then you'd likely need some narrowband filters on the receiving end to minimize the jitter.
[/quote]
I should shut up when I don't know what I'm talking about but it hasn't stopped me yet.
I am not advocating use of PLL to improve sync quality.
I still don't follow why DC level shifting with a passive cap coupler will introduce jitter, and it seems a sinusoidal master clock will increase sensitivity to jitter from noise (and ground issues, etc). If I'm the digital retard in the room ignore my confusion as it is apparently a personal problem.
[quote author="jdbakker"]
[quote author="JohnRoberts"][quote author="I"][...] dropped into a standard differential Cohen mic pre [...][/quote]
I'm still not sure why Cohen gets credit for that topology.[/quote]
I get the feeling that most people here know of the Cohen design (or the Green pre), so for me it's more a matter of using a commonly understood term than giving credit.
The much earlier version that I first saw (Transamp/Buff) doesn't pass DC offsets to the output so may be preferable for your app.
Do you mean like
the Valley People mic pre (as discussed in
this thread) ? I'll look into it, but I'm not too happy about the large cap/resistor values. I understand that the feedback should cancel most of the badness, but I'm still trying to see how a no-cap pre will sound (just like I want to know what an ADC sounds like when it's fed directly by a transformer).
JDB.[/quote]
Fine... I was just curious if Cohen had some priority I was not aware of. Especially since I've used variations since late '70s and like to know whose work to credit.
Agreed, the best cap is no cap. I have used both variants and can't say I've ever heard or measured any evidence of the cap inside the feedback loop other than loss of OL gain at very LF. FWIW I used much larger than Buff's .6 UF pushing the LF pole even lower.
In hindsight one negative aspect with Buff's version vs. non cap coupled versions is that DC coupled gain pot could alter input device current density if Vb-e not close. Biasing input though feedback resistors is less parts and excess noise from DC current will be quite small. If the loss of signal swing is an issue one could add current sources as in Buff's version.
My present inclination is to DC couple everything and use a servo (with nice characteristic film caps) between differential gain stage outputs to deal with input errors. A servo at the outputs should be a fair proxy for holding emitters close and dealing with external input offsets but like the early Buff version, voltage offsets will be corrected by forcing current differences in input devices (IIRC 1 dB current imbalance for every 3 mV voltage difference) so if large enough input correction applied may disturb some common mode performance due to device parameters. I haven't proven this on the bench so at this point it's just more mental masturbation.
JR
