Need help understanding a Chinese microphone circuit and troubleshooting

[skyy7]

A couple of other comments on the schematic as drawn -

• The C6/C7 junction isn't really connected to VL, is it? I would expect the bass roll-off switch to be connected between this junction and point H, so it bridges across C7 when closed.
• R8, the FET drain resistor, ought to be more than 1K. In most variants of this circuit it's 20K.

If it helps, there's a schematic for a similar FET configuration here: https://groupdiy.com/threads/mxl.84887/ which has measured DC voltages. If you're seeing anything wildly different it's probably a clue.

I am getting 34V at the end of the output inductors, 3.3V at the big 4.7u coupling capacitor, and 34.3V after R3 and R4. I don't see anything resembling R8 or R18 and 0V before and after C8. Nothing too weird besides the 0V at the source, which I'm assuming is very wrong... To confirm, I can swap the drain and the source, right?

 

[Voyager10]

Ok.... I have pin 3 connected to the 1Gohm resistor, pin 2 at C7, and pin 1 at R9. I think that's correct but I've made this mistake before so I wanna make sure. I was measuring 23.5V before C7, 0V before R9, and 2.5V before the 1Gohm resistor.

The pinout gives a view from below, so if you can imagine looking at the flat side of the package, with the pins pointing down, it will be souce-drain-gate, left to right.

In the picture, it looks like the source is the one connected to the 1G resistor.

 

[Voyager10]

To confirm, I can swap the drain and the source, right?

Yes, they can be swapped without affecting operation.

 

[Khron]

Yes, they can be swapped without affecting operation.

But wouldn't that mean that the Vgs(off) parameter is somehow "redundant" or meaningless? How does / can one bias a common-source stage for linear operation then?

I can understand the swappability of drain and source if the drain-source channel is in series with a signal, but otherwise.....

 

[skyy7]

I am so sorry... I didn't realize this entire time all those diagrams said bottom view...

The microphone now works. When I inject 1k 0.1v AC signal into the JFET I get 0.09% but when injecting it into R1 and R2 I get 8% THD. Is this normal?

If I were to bias using a pot, would pin 1 be at the end of R8, pin 2 at the end of the 1Gohm resistor, and pin 3 at the ground? Also, what is the purpose of having the inductors and the capacitors at the output? I thought both the inductor and the capacitor would do the same thing...

 

[Khron]

when injecting it into R1 and R2 I get 8% THD. Is this normal?

Where are "R1" and "R2"? Do remember none of us here are mind-readers, and that latest hand-drawn schematic of yours is missing half the component designators...

 

[skyy7]

Where are "R1" and "R2"? Do remember none of us here are mind-readers, and that latest hand-drawn schematic of yours is missing half the component designators...

Oh, sorry! R1 and R2 are the points the capsule connects to on the switch board. They labeled it a bit confusing as it sounds like a resistor.

 

[Khron]

Oh, sorry! R1 and R2 are the points the capsule connects to on the switch board.

That still means nothing. And the capsule has three wires; which one connects to the point you're describing?

 

[skyy7]

R1 connects to the front, R2 is the rear, and E is the backplate. It seems to connect to the gate of the J305 via a capacitor (C51 for the front and C52 for the rear) on the switchboard. G is the gate.

 

[Voyager10]

I am so sorry... I didn't realize this entire time all those diagrams said bottom view...

The microphone now works. When I inject 1k 0.1v AC signal into the JFET I get 0.09% but when injecting it into R1 and R2 I get 8% THD. Is this normal?

Good to hear it's now basically working.

If you are attaching a signal generator directly to the FET gate, it will control the DC bias level (to around 0V, presumably). R1 and R2 are capacitor-coupled to the gate, so the DC bias level will be determined by R12/R13 instead. So it appears the circuit is now working but the bias level is wrong.

You could quickly try putting a wire across R13 to tie the R12/R13 voltage to ground, so the gate bias is 0V. If this gets you "low" THD with the signal injected at R1 or R2, it confirms that it's just a bias issue.