New EE Lab - HF Design

[Ian MacGregor]

Well.. I just woke up after pulling an all-nighter. Apart from this lab, I am also taking 2 engineering courses, and writing course, and assistant engineering on a 12 song record being tracked in 6 days! I guess I can say I'm pretty spent!

Anyway, we talked to our professor and he liked the fact that we were trying to use a simple design. He did tell us that the MOSFET circuit would be inherently limited by the max rise time and we would not get the performance desired. He explained to uus how this was a Large-Signal AC problem and not a Small-Signal AC problem (which we known intuitively), but we have been taught mostly small signal and mistakenly were trying to use SS analysis to design our circuits.

We discussed the sample circuit he has given (the EF buffered diff pair). I asked him why it would work faster than a single EF buffered BJT switch. He told us to try it and see, because he really didn't know. I have a feeling he knows, but wants us to try.

Anyway, we built a BJT switch with a EF buffer, knocking down the input voltage so neither BJT will saturate. This configuration successfully drove the transmitting LED at speeds of 15-20MHz pretty well.

For our lab checkout (which is today), we must use the photodiode and see how much current it generates when driven by our Tx. We tested this last night and could not see much signal at all when using speeds above 100kHz or so.

Unfortunately, I will not be able to attend our checkout becuase I have to work (engineering record) so last night I asked my partner to double check that he knew how to hook up the circuit, show the teacher's assistant that it worked, etc. He proceeded to short the cathode of our transmitting LED ($14.00) to ground. I can't really be mad, because it was around 3am in the morning and we had both been awake since 9am.

I am not sure why we had pretty good high freq performance in the transmitter, but could not see signal from the recieving photodiode.

Thanks again for all your helps and ideas. Whether or not we successfully check out, I think we learned alot.

Ian

Oh yeah, the reciever amplifier is next, we are going to start on that soon!

 

[PRR]

> Did they not make 5pf caps back then?

When 30MC was "short wave", and you could only get there with L-C (not R-C): who needed 5 μμFd?

Anyway, you don't know how much you need until you try it. There will be several-pFd uncertainty in parasitic capacitance. And for tuned-circuit radio work, not a lot of tolerance, you have to tune a narrow passband TO the signal.

In good work, you could run a 22pFd screw-trimmer wide-open and get a few pFd.

In hasty benchwork, twisting a gimmick cap is quick and easy. And sometimes sturdy enough to go into production. Many many boxes had improvised custom gimmicks and flaps to add a few pFd here or there without making Cornell-Dubilier rich. Early FM radio and TV was full of tricks like this. UHF TV rotary tuners are all about pushing little bits of wire back or forth to get 0.1pFd more or less.

 

[skitch]

Hello all. I am Ian's diode-shorting lab partner and roomate. To start off I'd just like to thank everyone for all the help this (and last) quarter. We finished checking our project out today. Our final design is a common emitter BJT switch with emitter-follower buffering.
We were able to achieve 10MHz with a distinguishable high/low waveform. This is quite respectable considering we using only 2 transistors. Most groups didn't make it this high using the 4+ transistor differential circuit provided on the class website (I think Ian posted a link). We did hear indirectly from professor Rodwell (usually teaches this course unlike our current prof), that the differential stage is in fact faster than what we used. The TA's and even our current prof. could not explain the reason for this.
In the second part of the checkout we were required to measure the high and low output at the other end of the fiber-link (after the photodiode). Here we made it up to 5MHz which I think is substantial considering our fiber connection is 3ft in length. Don't ask me why Ian chose to use this long of link. Ther is no spec for lenth so we may end up shortening it substantially. I believe someone recommended a short link earlier. The longer the link the more loss and noise we get right?
Anways I'd like to thank all you for your help and wisdom (espcially PRR and bcarso). We'll keep you posted on the remainder of our project I'm sure. Peace.

 

[bcarso]

Thanks. The short link suggestion was just to allow a not-too-fancy receiver to be used while you were optimizing your transmitter, the point being that it's the photons not the current/voltage into/across the photodiode that ultimately count.

If you could please provide a link to what you ended up with as an LED driver.

 

[Svart]

BJTs SUCK FETS RULE!!


MUHA HA HA HA HA :twisted:


:green:

 

[PRR]

> the differential stage is in fact faster than what we used. The TA's and even our current prof. could not explain the reason for this.

Your version probably saturates. The diff-pair(s) version probably does not.

When you saturate a transistor (bang its collector all the way down almost to the emitter voltage), it becomes a very crappy transistor. Probably the worst problem for this assignment is "junction charge storage"; you should maybe read-up on that idea. Even at "mere" audio frequencies, if you saturate a transistor (usually by demanding an output as high as the supply rail, clipping), it takes a long time for it to stop conducting when the input drive is removed. The junction is "flooded" with charge, which has to be drained away before it will stop conducting. In audio, and in power inverters, charge storage can be a major problem already at 10KHz-50KHz. It is also why you don't use 1N1004 rectifiers above a few KHz: when the voltage "reverses", the diode keeps conducting. Your smaller-junction transistors can go faster, but still saturation is limiting the turn-off speed.

Long before you were born, we had a choice of RTL/TTL logic or ECL logic. RTL/TTL was cheap, but saturating. Saturation gave large solid logic-level swings and big fan-out, but (as in your case) went lame at a dozen MHz. Essentially the same transistors in ECL, which didn't saturate, would run 50MHz, but with lesser and more variable swing and higher power consumption. (And for general use, a need for an extra supply rail.)

The diff-pairs plan in the assignment is the core of an ECL logic gate. To be directly cascaded for general logic use, ECL had several more transistors to shift the level; not needed for a floating LED.

The flip-flops you were told to use are rated 4mA output. Ignoring the intent of the assignment (make you mess with discrete parts), I'd think about finding the hex-inverter in that series and paralleling the whole chip for 24mA drive, then use the LED specsheet R-C network. Assuming the chip is about the same price as several transistors, it would probably be a "better" commercial design, if only because it would be harder for some techie to probe carelessly and pop a transistor. (Most logic chips can be shorted forever.)

 

[bcarso]

If they are running at 6V the HC74 is capable of a tad more current while still meeting a specified logic level (5.2mA). But looking at the abs max Iout per pin of 25mA implies some caution. I suspect that's a CYA spec and based on power dissipation when all output pins might be similarly loaded, but why push it.

Using a 74HCU04 with the six sections in parallel would be one option---it's a good fast part, and with the intrinsic matching of a single chip wouldn't be too susceptible to a slow risetime input causing different inverters to contend with each other during the transition. If that were a problem the schmitt-trigger version 74HC14 could be used. But the lightly loaded Q outputs of the HC74 should be fast as blazes.

I would caution though about short-circuiting HC series parts--dissipation gets pretty high.

Another buffer that works well for driving MOSFET gates is a simple complementary emitter follower, with the bases simply tied together. NPN above, PNP below, emitters tied together. You lose a diode drop of voltage swing on each end, and there's a short delay while you traverse the Vbe's during the transition, and a bit of shoot-through current. Sims show a rise/fall time of about 1.5ns, driven from a 100 ohm Z source, but that is neglecting inevitable lead inductance etc. The SMD version and a tight layout would help. Also the gen rise/fall is only a nanosecond, that chosen to show what the stage itself is capable of. One reason why the stage is so fast is that the transistors cannot saturate---at worst the collector-base voltage is zero. It's a hard stage to beat within the limitations mentioned.

When driven from a much more pessimistic model of the CMOS output things get a lot lumpier and slower, but still producing decent swings at 25MHz. I'll try to get a more reasonable HC74 output stage model contrived.

(after some more work) Yes, with a pretty decent output stage model (40 ohm Ron, transconductance to match observed output current behavior with that Ron) the system slows down but is still pretty crisp at 25MHz. Rise and fall times to about 80% of each swing are still only about 2ns, but there is some complex structure for the last 15% or so of the transition.

Actually, it looks like the CMOS is doing the initial heavy lifting for the first few nanoseconds, coupling to the load through the base-emitter C's---3904's are not that superfast, and f beta is probably only about 6MHz, meaning that the current gain is commencing to fall a bunch beyond that.

 

[Ian MacGregor]

Ok, sorry for the delay (someone's gotta make rekkids!!), but here is the final circuit we used:

http://groupdiy.twin-x.com/albums/userpics/10021/final_tx.pdf

Thanks again for all of your help, we both really appreciate it. We will start on the recieving amplifier very soon!


Ian

 

[PRR]

I know why the plan shows Q7 Q8, but I'll rename them Q1 Q2.

They don't saturate. Brilliant!

The drive to Q1 comes from 22K||33K or 13K. That seems high for something that has to work at 10MHz-25MHz. Even 1pFd of stray capacitance will cause a droop; you probably have a dozen pFd or more.

Since your logic output can (and should) supply several mA at several volts, I'd take advantage of that to scale the input network more like 1K than 10K. Say 1K+1.5K?

Q1 will turn Q2 "on" real hard, but what turns Q2 "off"? That little 4.7K resistor? I'd use smaller values in audio. You have a lot of charge in that junction and it needs to be drained out fast to get Q2 and LED current to drop.

I'm wondering why Q1 is needed at all. If you make the input network like 1K5+1K5, omit Q1, then Q2 Base sees a nice low 750Ω for both turn-on and turn-off. The resulting input network current might not be too much for this class of CMOS.

Your LED idle current bleeder is 1mA; the LED datasheet shows more like 10mA idle. Your method gives greater DC output (at the photodiode) but does it give greater output at 10MHz-25MHz? The larger change in current is resisted by charge storage in the LED junction. I suspect at this point it makes little difference, but something to try. (Put not your faith in simulations, especially at extreme frequency with simple models.)