ok some tracing done..
all seems well in analog land except for the output..
imagine this, 4 channels use 12 coupling capacitors..
HOW? you ask..
Because the -output is impedence balanced, not true balanced.. it goes from connector to a ferrite to 120R straight to ground..
everything else is datasheet copy.
the digital board was replaced, I'm pretty sure of it.
The board now has a nice FPGA, a cpld, some memory, some proms and other assorted stuff. Seems that the clock is derived from the FPGA itself but there is a discrete PLL clock setup on the board that leads directly to I/O pins on the FPGA. I suppose the FPGA does the conversion for the various timings.
The voltage rails are derived from a SMPS on the analog board itself.. this part actually looks rather good. I bet the rails are nice and stable at least.
More on this later.