PRR said:> what I'm matching for now is the G1176
What is a 1176? Is that one of those FET limiters that is a 27K series resistor, a shunt JFET, and a bunch of other junk?
Why are you "matching"? Are you trying to lash two together for Stereo? Are you expecting them to track so well that there will be "no" image-shift while limiting? I suspect that this is extremely difficult; that you are fighting the normal variation from one FET to the next. My inclination would be to find out if there are any dual monolithic JFETs still available, and base your stereo design around the one part. FET parameters are so variable that any precision limiter will have enough adjustment to use about any FET. But doubling-up the adjustments to match two separate FETs gets harder to build and real hard to calibrate.
Set up a test rig similar to the actual circuit:
R1 should be equal to the series resistor used in the actual limiter.
V4 is a DC or AC source. It must be 100mV peak or less to stay within the FET's triode range. A 1.5V battery and a voltage divider to give 100mV will work. Or use an audio signal generator set for about 70mV RMS (100mV peak) output. Read the voltage from ground to the "V" symbol. For the DC source, you need a DC meter that will read 100mV down to a clear indication of 10mV; a 199mV digital voltmeter is barely good enough. For AC source you can read the output with a high impedance ACVM, or a high impedance audio amplifier (direct-box into a mike input) monitored with a VU or PPM meter. The audio technique can read in dB, which is intuitively what we want.
V1 is a 9V battery and a pot so we can put 0V to -9V DC on the Gate. Put a good DC voltmeter on the Gate.
Start without the FET. Trim your source so you get 100mV DC or 70mV AC at the "V" symbol. If you are using a VU meter, first use an ACVM to confirm about 70mV AC, then trim the mike amp so the VU meter reads 0 VU.
Put in an FET and trim the Gate voltage to -9V. You should still have the same voltage at "V". If not, check your connections.
Now trim the Gate voltage toward zero, slowly. Watch point "V". At some point it will drop 10%: 90mV DC, 63mV AC, or -1VU. Write down the Gate voltage needed to make this happen.
Now find the Gate voltage to make point "V" 50% or -6dB.
Now find the Gate voltage to make point "V" 10% or -20dB.
Insert another FET. Repeat.
The 90% or -1dB point is the 1dB Gain Reduction point. If you are just trimming a couple dB off the top, this is the most important test.
The 10% or -20dB point is of course 20dB GR. If you expect zero image shift in sustained heavy GR, this has to match very well.
For general use, all three points must match well. Also all points in between, but JFETs are predictable enough that if you match at -1dB, -6dB, and -20dB, it will probably be close everywhere else.
gemini86 said:the thing I like about PRR's simple approach is that it IS the 1176 circuit that the DUT (device under test) will be living in, so the results you get in the test jig are actual real world results. You can match fets at 1 point, but that doesn't make them matched at all if that isn't the constant operating point they'll be used at.
Chrome Heart said:So, does anyone see a problem with using the SPDT switch on the attack pot to short pad 22 to ground? Rev J board
gswan said:Exactly. The Vgs can be adjusted using a 25-turn trimmer between 0V and -5V, which is more than enough for these FETs. Measure Vgs at the points shown.
After measuring Vds, you can calculate Id using Id = ((+V - Vds)/10) mA
You can use a couple of 9V batteries instead of +/-10V to do this test, just measure the V+ value.
gswan said:They look fairly close, close enough to be easily trimmed.
Here's what I do for matching. Look at the graph of 10 devices, you can see a fair spread. Particularly look at the drain current when Vgs=0 and where the linear parts of the curve are.
http://www.axtsystems.com/index.php?option=com_content&view=article&id=46:1176lnfets&catid=34:1176ln&Itemid=62
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