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[quote author="mikep"][quote author="jdbakker"]
I've looked at doing just that. The main stumbling block (as far as I could see) is low-jitter master clock distribution. [/quote]
neumann tried to tackle this issue with their digital microphone, the D-01 (IIRC). I remember reading a paper about it a few years ago. AES-42 is the standard they came up with, might be worth a look.[/quote]
That's a very interesting solution to that particular problem, although in this day and age I'd more likely use an ASRC on the receiver end. You still get some EMI intermodulation, although much less than for free-running clocks (and it's less of an issue in the mics, which are physically further separated than the ADCs in a desk or recorder would be).

[quote author="Samuel Groner"]I edited the first post to include design D and E.[/quote]
Very nice. What transformer would you want to use ? Does transformer noise not make the 2SK170 overkill over direct coupling into the 5532 ? Oh, and you may want to include some switchable resistors in-line with the input signals to deal with low-Z microphones.

[quote author="ruffrecords"][...] and IME a gain of 40dB is more typical in real recording situations.[/quote]
You'd think so, but see this thread. I've seen similar dynamic range issues in live recordings.

JDB.
[who should stop posting and start finishing PCBs]
 
[quote author="jdbakker"][quote author="ruffrecords"][...] and IME a gain of 40dB is more typical in real recording situations.[/quote]
You'd think so, but see this thread. I've seen similar dynamic range issues in live recordings.[/quote]
If anything that supports my view that lower gains are more commonplace so output noise is more important than NF.

Ian
 
[quote author="ruffrecords"]
I am not sure why everyone gets so interested in very low noise transistors. Most modern types, whether PNP or NPN can give a mic preamp noise figure of between 1 and 3dB. You will probably need a PNP to get 1dB but 2dB is achieveable with NPN. This means the output noise is at most 3dB worse than the input noise at max gain. Unless you have a really low output mic or want to record something that is very quiet then the extra dB or two is not relevant. At that sort of gain, the self noise of most mics will exceed the mic pre noise anyway.

Plus, it is easy to design a mic pre with low noise figure at high gain. What is less easy is designing one that has a good noise figure at all gains. Manufacturers tend to quote NF at highest gain because that is dominated by input noise. Designers often think little about output noise which starts to dominate once the gain is reduced. For example suppose you have a pre with a -130dBu EIN. With a gain of 60dB the output noise (due to inout noise) is -70dBu. If the output noise is -80dB it won't significantly affect the total noise. But if you reduce the gain by 20dB, the noise at the output due to the input noise is -90dBu. The output noise at -80dBu now dominates and your wonderful input noise figure is wasted. A really good mic pre will be hard pushed to achieve better than -90dBu output noise so even with one of these output noise will dominate for gains less than 40dB and IME a gain of 40dB is more typical in real recording situations.

Ian[/quote]

I'm getting an education about how much GP devices have improved. No doubt process impurities have been reduced to facillitate finer geometries and better yield. It's all good.

Agreed wrt to noise vs. gain... In reviewing the appropriate gain to interface with a modern A/D is keeps moving down rather than up. Most A/Ds run from 5V rails so swing beyond that is wasted. Likewise the more bits of resolution offered the less gain required to line up mic noise floor with A/D noise floor.

A preamp designed for dedicated interface with A/D would probably benefit from smaller feedback Rs than a couple K, among other tweaks. In one DSP platform I did some work for I added a passive pad at the input to the A/D to better line up levels and swing but still not optimal.

Besides measuring noise at max gain, many also measure frequency response at low gain for the same reason (it looks better on paper).

JR
 
[quote author="jdbakker"]



[quote author="JohnRoberts"]Does cap coupling the clock cause actual jitter (an uncertainty from one clock to the next) or some fixed timing error due to C, perhaps interacting with device input C? This is beyond my understanding of things digital I guess but I don't see how a constant timing error from a passive component causes noise, variable timing errors sure.[/quote]
There are two different issues here. First:

[quote author="JohnRoberts"] [...] the last codec I worked with had a PLL that would just hunt and recover (I think... I never actually tried this with one).[/quote]
[quote author="I"]This approach works well, if you/your customers are content with 30..100ps clock jitter[/quote]
This 30..100ps clock jitter is mostly due to the use of PLLs. I know of no integrated audio PLL with typical clock jitter specs much better than 100ps. This is partly because many of them use on-chip ring oscillators or integrated LC VCOs, which have much lower Q than a crystal, and partly because it is hard (read:expensive) to build a phase comparator with a noise figure that is comparable to that of a good XO. If you know of any commercial PLLs which achieve much less than 30ps jitter on a 24.576MHz clock do let me know.

The other thing is:

[quote author="I"]The main stumbling block (as far as I could see) is low-jitter master clock distribution. The best I could think of was transformer coupling of the 24.576MHz MCLK into a low-noise limiting differential amplifier, but even that will easily double the jitter of a good low-noise clock source over impedance-matched DC coupling.
[/quote]

Assuming a good low-noise MCLK has 2.5ps jitter, sinusoid signal shape, 24.576MHz @ 3Vpp (LVCMOS), and the ADC clock input has its threshold exactly at mid-voltage. The slew rate at the switching point is

dV/dt = (2*pi*f*A)
= (2*pi*24.576M*(3V/2))
= 231MV/s = 231uV/ps

A little under 600uV (231*2.5) wideband noise is enough to double the 2.5ps jitter! With the supply servo it's likely that converter and backplane ground will have more noise between them than that, so single-ended capacitor coupling is out. Differential coupling is possible, but most semiconductor differential to single ended converters have a few ps jitter, too. So it's not the capacitors per se that are introducing the jitter, it's the whole clock chain. Some can be gained by using a clipped sine as that speeds up the edge rate, but this introduces harmonics and makes the system sensitive to group delay. RF transformers work best, but even then you'd likely need some narrowband filters on the receiving end to minimize the jitter.
[/quote]

I should shut up when I don't know what I'm talking about but it hasn't stopped me yet.

I am not advocating use of PLL to improve sync quality.

I still don't follow why DC level shifting with a passive cap coupler will introduce jitter, and it seems a sinusoidal master clock will increase sensitivity to jitter from noise (and ground issues, etc). If I'm the digital retard in the room ignore my confusion as it is apparently a personal problem.

[quote author="jdbakker"]
[quote author="JohnRoberts"][quote author="I"][...] dropped into a standard differential Cohen mic pre [...][/quote]

I'm still not sure why Cohen gets credit for that topology.[/quote]

I get the feeling that most people here know of the Cohen design (or the Green pre), so for me it's more a matter of using a commonly understood term than giving credit.

The much earlier version that I first saw (Transamp/Buff) doesn't pass DC offsets to the output so may be preferable for your app.

Do you mean like the Valley People mic pre (as discussed in this thread) ? I'll look into it, but I'm not too happy about the large cap/resistor values. I understand that the feedback should cancel most of the badness, but I'm still trying to see how a no-cap pre will sound (just like I want to know what an ADC sounds like when it's fed directly by a transformer).

JDB.[/quote]

Fine... I was just curious if Cohen had some priority I was not aware of. Especially since I've used variations since late '70s and like to know whose work to credit.

Agreed, the best cap is no cap. I have used both variants and can't say I've ever heard or measured any evidence of the cap inside the feedback loop other than loss of OL gain at very LF. FWIW I used much larger than Buff's .6 UF pushing the LF pole even lower.

In hindsight one negative aspect with Buff's version vs. non cap coupled versions is that DC coupled gain pot could alter input device current density if Vb-e not close. Biasing input though feedback resistors is less parts and excess noise from DC current will be quite small. If the loss of signal swing is an issue one could add current sources as in Buff's version.

My present inclination is to DC couple everything and use a servo (with nice characteristic film caps) between differential gain stage outputs to deal with input errors. A servo at the outputs should be a fair proxy for holding emitters close and dealing with external input offsets but like the early Buff version, voltage offsets will be corrected by forcing current differences in input devices (IIRC 1 dB current imbalance for every 3 mV voltage difference) so if large enough input correction applied may disturb some common mode performance due to device parameters. I haven't proven this on the bench so at this point it's just more mental masturbation.

JR
 
[quote author="JohnRoberts"]I still don't follow why DC level shifting with a passive cap coupler will introduce jitter[/quote]
It's a distant cousin to the infamous pin 1 problem. You're not just level shifting, you're level shifting to a floating power domain. It's non-trivial to keep AC coupling tight enough to eliminate noise, especially if you have several such power domains (as every input needs its own domain). The best you could do with capacitor coupling is something like ECL (which is differential) across the gap. This still costs a few ps in jitter end-to-end.

[quote author="JohnRoberts"]and it seems a sinusoidal master clock will increase sensitivity to jitter from noise (and ground issues, etc).[/quote]
True, getting faster edges helps. However, the lowest-noise oscillators have a sinusoidal output, and any method to 'square up' the signal will have to be non-linear. Most of these add jitter through noise or non-harmonic distortion. One of the more benign ways to get faster edges is to slightly overdrive the ADC's MCLK input, just at or below the point where the converter's protection diodes start conducting.

JDB.
[with bad memories of a phased-array antenna processing system. All channels needed to be isolated to satisfy some arcane gov't regulations, and all channels needed a common clock. It was a Fun Learning Experience]
 
[quote author="mediatechnology"]Seems like a linear offset stage would be the most direct way to keep things pure analog until we need it quanitized.[/quote]
Oh, I agree. Use a pair of coupling caps, a servo-controlled DC shifting op-amp or even a transformer. This all started with JR remarking om page three that

[quote author="JohnRoberts"]I would be surprised if somebody hasn't already flown a pre and A/D up there then passed the digital output via optical...[/quote]
As far as I'm concerned, the ADC is how it could be done. Like you say, other methods may be a better fit for any particular scenario.

JDB.
 
[quote author="jdbakker"][quote author="JohnRoberts"]I still don't follow why DC level shifting with a passive cap coupler will introduce jitter[/quote]
It's a distant cousin to the infamous pin 1 problem. You're not just level shifting, you're level shifting to a floating power domain. It's non-trivial to keep AC coupling tight enough to eliminate noise, especially if you have several such power domains (as every input needs its own domain). The best you could do with capacitor coupling is something like ECL (which is differential) across the gap. This still costs a few ps in jitter end-to-end.

[quote author="JohnRoberts"]and it seems a sinusoidal master clock will increase sensitivity to jitter from noise (and ground issues, etc).[/quote]
True, getting faster edges helps. However, the lowest-noise oscillators have a sinusoidal output, and any method to 'square up' the signal will have to be non-linear. Most of these add jitter through noise or non-harmonic distortion. One of the more benign ways to get faster edges is to slightly overdrive the ADC's MCLK input, just at or below the point where the converter's protection diodes start conducting.

JDB.
[with bad memories of a phased-array antenna processing system. All channels needed to be isolated to satisfy some arcane gov't regulations, and all channels needed a common clock. It was a Fun Learning Experience][/quote]

Thanks I can follow that... grounds are not very good across a few inches of ground plane so floated tens of volts away local grounds and therefore logic thresholds will be hard to bond. Differential treatment of clock signal adds more active devices to add noise.

Seems like you need to run your system clock up to +/- 15v for clearer distribution. Of course you would want to do that as a sine wave to keep the FCC from knocking on your door (just kidding).

At the risk of asking another stupid question how much jitter is a typical 24 MHz crystal? After you have a clean A/D conversion the integrity of the audio should be fairly robust, but I guess there's always ways to corrupt anything and too many similar crystals could beat. Interesting stuff.

JR
 
The interaction with the input coupling caps is fixable by making the time constant of the servo sufficiently larger than that of Rin*Cin. A factor of 10 is usually enough, in my experience.
True. Things start to become difficult though if you want the input coupling capacitors to be large in order to minimise 1/f noise and to get best LF CMRR. In design A and C, the common-mode -3 dB frequency is at 16 mHz... How did you size your input RC network?

Yes, please! Mine is rather inspired by your DOA as it is, and I'm looking to design a pre not a DOA.
-> PM.

For a rough idea, take the SGA-SOA, add a collector resistor to Q2, duplicate the gain and output stages (Q4-Q7) to get a negative output, and add a regular op-amp to set the common mode voltage on the output.
Cool! :thumb:

I am not sure why everyone gets so interested in very low noise transistors. Most modern types, whether PNP or NPN can give a mic preamp noise figure of between 1 and 3 dB.
I guess you mean by paralleling devices? A BC560C has a rbb of 155 ohm @ 2 mA according to the ON Semi datasheet, which pretty successfully prevents a 3 dB noise figure (for 150 ohm) without paralleling. Other things to consider include low 1/f voltage and current noise as well as low sample variations regarding noise parameters.

Plus, it is easy to design a mic pre with low noise figure at high gain. What is less easy is designing one that has a good noise figure at all gains. Manufacturers tend to quote NF at highest gain because that is dominated by input noise. Designers often think little about output noise which starts to dominate once the gain is reduced. For example suppose you have a pre with a -130 dBu EIN. With a gain of 60 dB the output noise (due to inout noise) is -70 dBu. If the output noise is -80 dB it won't significantly affect the total noise. But if you reduce the gain by 20 dB, the noise at the output due to the input noise is -90 dBu. The output noise at -80 dBu now dominates and your wonderful input noise figure is wasted. A really good mic pre will be hard pushed to achieve better than -90 dBu output noise so even with one of these output noise will dominate for gains less than 40 dB and IME a gain of 40 dB is more typical in real recording situations.
I very much agree with you on the relevance of medium gains regarding noise. Note however that your -80 dBu output noise figure is way off. A quick calculation indicated that e.g. design A and C have an output related noise of -108 dB typically, which is an outright different order than what you expected. Note as well that input related noise gets worse as well at lower gains as the feedback network impedance rises.

What transformer would you want to use?
Personally I'd go with a Jensen JT-13K7-A, very good overall performance.

Does transformer noise not make the 2SK170 overkill over direct coupling into the 5532?
I don't think so--you get lower voltage noise and (more important) very low current noise. Many dynamic microphones seem to have an inductive output impedance rising to 600 ohm at a few kHz, resulting in a substantial increase in HF noise if used with high current noise inputs. Another advantage is that we have a current-feedback amplifier again in the first stage, providing less variation in distortion and BW as gain varies. I should have noted in the schematic though that it is well possible to use this design with lower-ratio transformers. In addition to this, the output has wrong polarity as shown (copy-past error from design D)--I'll do an update ASAP ([edit] PDF updated.).

Samuel
 
[quote author="JohnRoberts"]Agreed wrt to noise vs. gain... In reviewing the appropriate gain to interface with a modern A/D is keeps moving down rather than up. Most A/Ds run from 5V rails so swing beyond that is wasted. Likewise the more bits of resolution offered the less gain required to line up mic noise floor with A/D noise floor.[/quote]
Another good reason why output noise is important. 5V peak to peak is about 1.76V rms or +7dBu. Our top notch mic pre with -90dBu output noise has a max dynamic range of 97dB - not much use with a 24bit AtoD.. That is one good reasons why 24bit AtoDs need redesigning to work from +-15V rails which even then only gives 108dB dynamic range - greater than that needs low gain very low output noise preamps - not a regular mic pre as you rightly point out.

Ian
 
Samuel Groner said:
I very much agree with you on the relevance of medium gains regarding noise. Note however that your -80 dBu output noise figure is way off. A quick calculation indicated that e.g. design A and C have an output related noise of -108 dB typically, which is an outright different order than what you expected. Note as well that input related noise gets worse as well at lower gains as the feedback network impedance rises.
Samuel
I would not say -80dBu was way off - there are loads of mic pres out there that do little better. When I was at Neve in the 70s, -90dBu was about the best we could achieve. I know technology has moved on but fundamental physics is unchanged so I will definitely check the output noise figures for designs A and C.

Ian
 
[quote author="ruffrecords"]
I would not say -80dBu was way off - there are loads of mic pres out there that do little better. When I was at Neve in the 70s, -90dBu was about the best we could achieve. I know technology has moved on but fundamental physics is unchanged so I will definitely check the output noise figures for designs A and C.

Ian[/quote]

An old axiom about business management is that when you measure things they magically improve.. No magic of course and I suspect many of the topologies described can be quite good if dialed in for 5V output and lower gains.

To provide some food for thought the Johnson or thermal noise of a 150-200 ohm resistor is something like -132 dBu (from memory). I recall 50 ohm nominal mics from the old days of film before wireless mics to deal with very long wire runs, but suspect the output scaled down with impedance. If a 24b digital word is capable of 144 DB dynamic range, in theory, it seems like the gain needed to line up are modest indeed. Note: audio doesn't hit a brick wall at this noise floor and can be perceived several dB lower so perhaps useful to capture a couple bits below this level.

(EDIT: It's also worthwhile noting that high bit A/D often have noise floors higher than their LSB. Perhaps worthwhile to line up mic Johnson noise to A/D noise floor or slightly above)

Perhaps a better way to look at this wrt preamp design is NF or noise contribution vs a perfect noiseless gain stage. A 40 dB gain stage with -90 dBu noise floor is right there (re NF at 200 ohm). Likewise a 60dB gain stage with much better than -70 dBu output noise is suspect. One cheat on data sheets is to measure with input shorted which may not reliably predict noise performance with real mics.

I suspect the true benefit to be derived from long word lengths in the digital domain is for protection from overload when combining multiple signals and for various signal processing math resolution.

I am not smart enough about microphone technology to know what the real limits are for sensitivity and noise floor but it seems modern mic preamp topologies could be dialed in to perform well if thoughtfully applied (optimized at right gain etc).

I have even pondered making some parameters of mic preamps adjustable (input current density, specific phantom voltage, specific input termination, etc) to maybe milk that last dB of S/N out of a mic (Note: playing with termination impedance may have undesired influence on frequency response).

To some extent this is counting angels on a pin head as many other things make larger impact on final quality of recordings, but an interesting mental exercise none the less.

JR
 
[ummm... Wayne, what's with the loud avatar ?]

[quote author="Samuel Groner"]How did you size your input RC network?[/quote]
Between 10k and 22k per leg, IIRC, with 47..100u input capacitance (although I have some 3u3 polycarb caps coming in that I need to audition).

Why do you use 100k input bias resistors in A and C ? Unless you switch out both 6k81 resistors there isn't much difference in CM impedance between 22k and 100k.

[quote author="JohnRoberts"]how much jitter is a typical 24 MHz crystal?[/quote]
How much distortion does a typical 1:2 mic input transformer produce ?

It depends. The main factor that determines crystal-related jitter is its Q. Like any resonant structure (such as those used in EQs), a crystal has a quality factor Q, which IIRC is the ratio between center frequency and -3dB-bandwidth. I have checked a few datasheets, and manufacturers don't ordinarily specify this; according to the literature it is in the order of a few tens of thousands. The Q determines how much phase noise there is; by integrating the phase noise over the frequency range of interest you can determine the jitter.

But that's just the crystal. Most crystals need parallel capacitance to get the right frequency of operation. Any oscillator will need an amplifier; the loading by this active element will affect Q. Amplifier noise impacts jitter as well. There are dozens of oscillator configurations, some are more jitter sensitive than others. And then there is supply noise, load-induced noise, microphonics...

One general trend is that higher-frequency oscillators will have less jitter when measured in absolute units (i.e. ps). I'm trying to figure out if a 155/622MHz communications-grade oscillator combined with a Direct Digital Synthesizer, as proposed in this Analog Devices appnote, might make sense for an audio system.

[quote author="JohnRoberts"]It's also worthwhile noting that high bit A/D often have noise floors higher than their LSB. Perhaps worthwhile to line up mic Johnson noise to A/D noise floor or slightly above.[/quote]
Indeed, let's not focus so much on the mic pre that we forget the performance of the entire system. State of the art ADCs have a dynamic range of 120dB, give or take. Take the CS5381: 0dBFS is 2Vrms, its noise floor is ~2uVrms. 150 Ohm in 20Hz-20kHz is about 200nVrms, so about 20dB below the converter's noise floor. No matter how low the mic pre's noise figure, at a gain of 20dB the system noise figure can be no better than 3dB. Conversely there is little point in a mic pre gain over 40dB since mike noise will dominate the converter's noise, and all you achieve by increasing gain is reducing headroom.

[quote author="JohnRoberts"]To some extent this is counting angels on a pin head as many other things make larger impact on final quality of recordings, but an interesting mental exercise none the less.[/quote]
I do mostly live recordings. As the stage manager of one recent venue said to me recently: "How many dB does your mike's noise floor really need to be below the sound from our HVAC systems ?"

JDB
[and happy happy joy joy to y'all for 2007]
 
I would not say -80 dBu was way off - there are loads of mic pres out there that do little better. When I was at Neve in the 70s, -90 dBu was about the best we could achieve.
Obviously I cannot comment on designs which I have not measured nor seen a schematic of, but I just dug out some measurement notes from the Millennia Media HV-3D, and the numbers at the lowest gain setting (+8 dB) were -100 dBu (50 ohm source) and -99.5 dBu (150 ohm source), that is at 20 kHz BW. Another much less know high-quality transformerless design made it to -100 dBu at 0 dB gain, independent of source impedance.

I know technology has moved on but fundamental physics is unchanged so I will definitely check the output noise figures for designs A and C.
I'm not sure why you think that physics should limit reasonable design to -80 dBu--that is the thermal noise of a 18 Mohm (Mega!) resistor, and there's hardly any reason to put such a resistor in series with the output stage. Can you elaborate?

[Edit: I think I might have an idea where your -80 dBu/-90 dBu figure comes from; 70s sounds like a transformer balanced design with PAD in front, which likely results in the figures you quoted. But not because output related noise is that bad, but rather because the input stage is still running at considerable gain.]

Why do you use 100k input bias resistors in A and C? Unless you switch out both 6.8k resistors there isn't much difference in CM impedance between 22k and 100k.
Yes, but the coupling capacitors (read: their 20% tolerance) see the 100k only. Sure, the CMRR improvement within the audio band might be marginal, but as there is no serious disadvantage either (I never planned to use a servo with design A and C), I feel happy with the 100k. Some other designs even start to bootstrap a ~100k resistance there, which I never understud... [Edit: actually my main reason to have 100k there was to not compromise the 0.1% precision of the 6.8k resistors.]

Samuel
 
After careful study of the interesting THAT AES paper I decided to change the protection of design A, B and C to a more robust standard. In addition to this, I updated all zener clamps on the supply rails from 1 W to 5 W. Now we should be ready for serious real-world abuse! Thanks for the advice and the discussion so far--I find it very illuminative to hear others opinion on my designs (although I usually have many arguments ready to support my point of view :grin: ).

Samuel
 
I'm not sure we're on the same page here.. I don't know about LF capacitor distortion as in a non-linearity, but the expected ESR and ESL (perhaps DF?) will be an issue just like using electrolytics in a passive speaker crossover. Into 2 ohms at "high" frequency it will not be a very ideal capacitor.
I missed this post earlier. www.dself.dsl.pipex.com/ampins/dipa/dipa.htm (bottom of the page) e.g. has some info on capacitor distortion, as does Jung in his "Picking Capacitors" (online somewhere).

Samuel
 
[quote author="Samuel Groner"]
I'm not sure we're on the same page here.. I don't know about LF capacitor distortion as in a non-linearity, but the expected ESR and ESL (perhaps DF?) will be an issue just like using electrolytics in a passive speaker crossover. Into 2 ohms at "high" frequency it will not be a very ideal capacitor.
I missed this post earlier. www.dself.dsl.pipex.com/ampins/dipa/dipa.htm (bottom of the page) e.g. has some info on capacitor distortion, as does Jung in his "Picking Capacitors" (online somewhere).

Samuel[/quote]
Sorry, this is mostly speculation on my part based on seeing a 6800uF in the gain leg. From a quick web search there are some new series of low impedance electrolytic caps with ESL down in the hundreds of pico-Henrys so perhaps I’m all wet, but I would be nervous about HF/high gain phase shift with that large of a cap in the gain leg. My bench experience with phase shift in such applications is a few decades old and perhaps dated.

Yes, I’m aware of the distortion mechanism Self describes, perhaps better known as “voltage coefficient”. Yes increasing the capacitance will push down the pole frequency and reduce expression of that mechanism at the low end, however I remain concerned about ESL/ESR in that particular circuit node.

By all means don’t use common electrolytics in series with power amp outputs or speaker crossovers. At the risk of stereotyping Jung, I haven’t followed him for a few decades so will make no comments about my old impressions of his early work.

I like the effort to eliminate capacitors when possible. When you do use them, their non-ideal characteristics are sometimes obscure but not that mysterious. It is entirely possible to degrade one parameter while improving another.

I may also be full of poop about this particular one. Easy enough to disprove by comparing phase shift at 20 kHz for min and max gains.

JR
 
[quote author="JohnRoberts"][quote author="ruffrecords"]
I would not say -80dBu was way off - there are loads of mic pres out there that do little better. When I was at Neve in the 70s, -90dBu was about the best we could achieve. I know technology has moved on but fundamental physics is unchanged so I will definitely check the output noise figures for designs A and C.

Ian[/quote]
To provide some food for thought the Johnson or thermal noise of a 150-200 ohm resistor is something like -132 dBu (from memory). I recall 50 ohm nominal mics from the old days of film before wireless mics to deal with very long wire runs, but suspect the output scaled down with impedance. If a 24b digital word is capable of 144 DB dynamic range, in theory, it seems like the gain needed to line up are modest indeed. Note: audio doesn't hit a brick wall at this noise floor and can be perceived several dB lower so perhaps useful to capture a couple bits below this level. [/quote]
It is worth adding two others point here - first the ear has a dynamic range of about 140dB which lines up quite nicely with the theroretical resolution of 24 bits. The second is that tests have shown people can typically hear signals 14 to 18dB below the noise floor. That's why resolution in digital systems is important and why dithering is essential.

(EDIT: It's also worthwhile noting that high bit A/D often have noise floors higher than their LSB. Perhaps worthwhile to line up mic Johnson noise to A/D noise floor or slightly above)

Usually a long way above. Most are limited by the noise perfomance of their own internal analog parts - I don't think I have seen one yet that does better than -120dFS.

Ian
 
[quote author="ruffrecords"]
It is worth adding two others point here - first the ear has a dynamic range of about 140dB which lines up quite nicely with the theroretical resolution of 24 bits. The second is that tests have shown people can typically hear signals 14 to 18dB below the noise floor. That's why resolution in digital systems is important and why dithering is essential.
========

Usually a long way above. Most are limited by the noise perfomance of their own internal analog parts - I don't think I have seen one yet that does better than -120dFS.

Ian[/quote]

I'm not sure if this is your point but the analog noise floor in the A/D will dither any lower level bits. As compared to dithering with 1/2 LSB to unlock some lower information.

I'm not sure how important information is much below the noise floor but another way to look at this is quantization distortion to audio just below this noise floor may indeed be audible through the noise justifying a few bits down there.


JR
 
I like what you did with drawings A and C to pre-bias the input coupling caps. It's similar to what SSL did in the 82E149 but with only a pair of Cs.
All the later Neve stuff I've seen does it as well, with two caps. No idea why he didn't switch to PNP inputs, would have made things much easier..?

Design F now online--see first page!

There was a small error in schematic E--the voltage rating for C4 and C5 is obviously 6.3 V and not 63 V. PDF updated.

Samuel
 
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